“ I am very glad for this opportunity to interact with the student community and share my experience through this workshop. I have personally designed this workshop agenda, after long contemplation on the needs of fresh electronics engineering students.
I am sure this workshop will help the attendee to understand the concepts of RTL design using Verilog HDL and also gain the hand on experience. So, participate in this workshop, interact with me and learn from my experience. This workshop will help if you are very passionate about VLSI technology and want to work in the Chip Design Industry.
Looking forward to meeting you all through this workshop. “
“ I am so glad to utilise this opportunity to interact with you and share my experience. I have personally designed this verification workshop agenda after a long contemplation and I am sure this interactive session will address all your queries about the latest verification trends.
In addition to latest methodologies, I will also explain our product architecture ABLE5 - Aceic's Bluetooth Low Energy 5.0 Verification IP. This will help you to understand 'Why System Verilog and UVM' and how you can accelerate your verification process using latest verification methodologies. So participate, interact and learn from my experience. Also I expect you to share your experience with us. Looking forward to meeting you all during this workshop. “