ASIC Verification Course

Module 1

Advanced Digital

• Combinational Circuits - Design and Analysis
• Sequential Circuits - Design and Analysis
• Shift Registers and Counters
• Finite State Machine

Module 2

Introduction to Linux

• Components of UNIX system
• Directory Structure
• Utilities and Commands
• Vi Editor

Module 3

Static Timing Analysis

• Introduction to STA
• Comparison with DTA
• Timing Path and Constraints
• Different types clocks
• Clock domain and Variations
• Clock Distribution Networks
• How to fix timing failure

Module 4

Advanced Verilog for verification

• Tasks and Functions
• Delays - Regular, Intra Assignment
  and Intertial Delays
• Race Conditions
• File I/O operation
• TB Constructs
• Self checking Testbenches

Module 5

Code Coverage

• Statement coverage
• Branch Coverage
• Expression Coverage
• Path Coverage
• Toggle Coverage
• FSM - State, Arc and Sequence coverage

Module 6

ASIC Verification Methodologies

• Directed Vs Random
• Functional verification process
• Stimulus Generation
• Bus function model
• Monitors and reference models
• Coverage Driven Verification
• Verification Planning and management

[1] Introduction to System Verilog

• New Data types
• Tasks and Functions
• Interfaces
• Clocking Blocks

[2] Object Oriented Programming and Randomization

• OOP Basics
• Classes - Objects and handles
• Polymorphism and Inheritance
• Randomization
• Constraints

[3] Threads and Virtual Interfaces

• Fork Join
• Fork Join_any
• Fork Join_none
• Event controls
• Mailboxes and semaphores
• Virtual Interfaces
• Transactors
• Building verification environment
• Test cases

[4] Callbacks

• Facade Class
• Building Reusable Transactors
• Inserting Callbacks
• Registering Callbacks

[5] Direct Programming Interface

[6] Functional Coverage

• Coverage models
• Coverpoints and bins
• Cross coverage
• Regression testing

Module 8

Advanced System Verilog

• Environment Configuration
• Reference Models and Predictor Logics
• Using Legacy BFMs
• Scenario Generation
• Testcases - Random, Directed and
  Corner Case
• Coding styles for VIP

Module 9

Verification Planning and Management

• Verification Plan
• TB Architecture
• Coverage Model
• Tracking the simulation process
• Building regression testsuite
• Testsuite optimization

Module 10

Assertion Based Verification - SVA

• Introduction to ABV
• Immediate Assertions
• Simple Assertions
• Sequences
• Sequence Composition
• Advanced SVA Features
• Assertion Coverage

Module 11

UVM-Universal verification
Methodology

• Introduction to UVM Methodology
• Overview of Project
• UVM TB Architecture
• Stimulus Modeling
• Creating UVCs and Environment
• UVM Simulation Phases
• Testcase Classes
• TLM Overview
• Configuration TB Environment
• UVM Sequences
• UVM Sequencers
• Connecting DUT - Virtual Interface
• Virtual Sequences and Sequencers
• Creating TB Infrastructure
• Connecting multiple UVCs
• Building a Scoreboard
• Introduction to Register Modeling
• Building reusable environments

Module 12

Design Automation using Scripts Perl

• Introduction to Perl
• Functions and Statements
• Numbers, Strings, and Quotes
• Comments and Loops

Module 13

Pilot project - Verification and RTL Sign-off

• Project Specification Analysis
• Understanding the architecture
• Module level implementation and verification
• Building the top level module

Module 14

Industry Standard Project

• Project specification analysis
• Defining verification plan
• Creating Testbench architecture
• Defining Transaction
• Implementing the transactors - Generator, Driver, Receiver and Scoreboard
• Implementing the coverage model
• Building the top level verification environment
• Defining weighted random, corner case and directed
• Building the functional and
  code coverage reports

EDA TOOLS

• Mentor Graphics

OPERATING SYSTEMS

• Linux - Ubuntu