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Advanced ASIC Verification Course

Designed & delivered by Industry Experts

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ASIC Verification Course

Decade of
Excellence

SystemVerilog Training

Highly expert faculty
with 20+ yrs of avg exp

Highly rated course 850+ Google reviews | 4.6 Rating

Highly rated course
850+ Google reviews | 4.6 Rating

40K+ Learners on Online Platform

40K+ Learners on
Online Platform

ASIC Verification Course

250+ Industry
Partners

SystemVerilog Training

3500+
Alumni

What is VLSI VM?

The Advanced ASIC verification course [VLSI VM] trains the engineers extensively on the Verification methodologies and help them to join the industry as ASIC Verification Engineer. The key features of the ASIC Verification course are ASIC Verification Methodologies, Advanced Verilog for Verification, SystemVerilog, UVM, Assertion Based Verification - SVA, Verification Planning and Management, Code and Functional Coverage, Perl scripting language and VIP coding style.

5 Months Training + 6 Months Internship

Full time | Blended | Part time

Why join VLSI VM?
(Very Large-Scale Integration - RTL to Netlist)

This advanced course on ASIC Verification with 100% placement assistance offers the high-class training on latest verification skills i.e. SystemVerilog, Assertion Based Verification SVA, UVM along with Internship from Industry perspective and makes you a ready-to-deploy ASIC Verification Engineer.

Our CEO Mr. P R Sivakumar explains, how VLSI VM course can help you build your skills set and get a job in semiconductor industries.

Key Features of VLSI-VM

Course Features

  • Training and Internship
  • Advanced Logic Design
  • ASIC Verification Methodologies
  • Advanced Verilog for Verification
  • HVL: SystemVerilog
  • Verification Methodology: UVM
  • Assertion Based Verification: SVA
  • Verification Planning and Management
  • Code and Functional Coverage
  • Scripting - Perl
  • Coding styles for VIPs
  • Pilot Projects
  • Industry Standard Project
  • Operating System - Linux
  • RISC-V Instruction Set Architecture
  • RISC-V RV32I RTL Architecture Design

Internship Projects

  • AHB2APB Bridge RTL
  • PCS Subsystem RTL design
  • SPI IP core RTL Design
  • UART IP core RTL Design
  • AHB UVC - Master agent in UVM
  • AHB2APB Bridge Verification in UVM
  • UART IP Verification in UVM
  • AHB UVC - Slave agent in UVM
  • GPIO Verification in UVM
  • PCS subsystem IP Verification - UVM
  • AXI UVC - Master agent in UVM
  • I2C Real Time Clock IP design
  • ICPIT Verification in UVM
  • AXI UVC - Slave agent in UVM
  • SPI IP Verification - UVM
  • RISC-V Verification in UVM
  • Bluetooth VIP in UVM

Elective Modules

  • LP - Low Power VLSI Design
  • DFT - Design For Testability
  • AMS - Analog Mixed Signal

EDA Tools

  • Mentor Graphics
  • Xilinx
  • Aldec

Curriculum

The dynamic curriculum of Advanced ASIC Verification Course fits perfectly with the career aim of fresh engineering graduates and helps them to ‘future-proof’ themselves and remain relevant for the rapidly evolving Semiconductor technology space.

MODULE 1

Advanced Digital

  • Combinational Circuits - Design and Analysis
  • Sequential Circuits - Design and Analysis
  • Shift Registers and Counters
  • Finite State Machine

MODULE 2

Introduction to Linux

  • Components of UNIX system
  • Directory Structure
  • Utilities and Commands
  • Vi Editor

MODULE 3

Static Timing Analysis

  • Introduction to STA
  • Comparison with DTA
  • Timing Path and Constraints
  • Different types clocks
  • Clock domain and Variations
  • Clock Distribution Networks
  • How to fix timing failure

MODULE 4

Advanced Verilog for verification

  • Tasks and Functions
  • Delays - Regular, Intra Assignment and Inertial Delays
  • Race Conditions
  • File I/O operation
  • TB Constructs
  • Self checking Testbenches

MODULE 5

Code Coverage

  • Statement coverage
  • Branch Coverage
  • Expression Coverage
  • Path Coverage
  • Toggle Coverage
  • FSM - State, Arc and Sequence coverage

MODULE 6

ASIC Verification Methodologies

  • Directed Vs Random
  • Functional verification process
  • Stimulus Generation
  • Bus function model
  • Monitors and reference models
  • Coverage Driven Verification
  • Verification Planning and management

MODULE 7

[1] Introduction to System Verilog

  • New Data types
  • Tasks and Functions
  • Interfaces
  • Clocking Blocks

[2] Object Oriented Programming and Randomization

  • OOP Basics
  • Classes - Objects and handles
  • Polymorphism and Inheritance
  • Randomization
  • Constraints

[3] Threads and Virtual Interfaces

  • Fork Join
  • Fork Join_any
  • Fork Join_none
  • Event controls
  • Mailboxes and semaphores
  • Virtual Interfaces
  • Transactors
  • Building verification environment
  • Test cases

[4] Callbacks

  • Facade Class
  • Building Reusable Transactors
  • Inserting Callbacks
  • Registering Callbacks

[5] Direct Programming Interface

[6] Functional Coverage

  • Coverage models
  • Coverpoints and bins
  • Cross coverage
  • Regression testing

MODULE 8

Advanced System Verilog

  • Environment Configuration
  • Reference Models and Predictor Logics
  • Using Legacy BFMs
  • Scenario Generation
  • Testcases - Random, Directed and
    Corner Case
  • Coding styles for VIP

MODULE 9

Verification Planning and Management

  • Verification Plan
  • TB Architecture
  • Coverage Model
  • Tracking the simulation process
  • Building regression testsuite
  • Testsuite optimization

MODULE 10

Assertion Based Verification - SVA

  • Introduction to ABV
  • Immediate Assertions
  • Simple Assertions
  • Sequences
  • Sequence Composition
  • Advanced SVA Features
  • Assertion Coverage

MODULE 11

UVM-Universal verification
Methodology

  • Introduction to UVM Methodology
  • Overview of Project
  • UVM TB Architecture
  • Stimulus Modeling
  • Creating UVCs and Environment
  • UVM Simulation Phases
  • Testcase Classes
  • TLM Overview
  • Configuration TB Environment
  • UVM Sequences
  • UVM Sequencers
  • Connecting DUT - Virtual Interface
  • Virtual Sequences and Sequencers
  • Creating TB Infrastructure
  • Connecting multiple UVCs
  • Building a Scoreboard
  • Introduction to Register Modeling
  • Building reusable environments

MODULE 12

Design Automation using Scripts Perl

  • Introduction to Perl
  • Functions and Statements
  • Numbers, Strings, and Quotes
  • Comments and Loops

MODULE 13

Pilot project - Verification and RTL Sign-off

  • Project Specification Analysis
  • Understanding the architecture
  • Module level implementation and verification
  • Building the top level module

MODULE 14

Industry Standard Project

  • Project specification analysis
  • Defining verification plan
  • Creating Testbench architecture
  • Defining Transaction
  • Implementing the transactors - Generator, Driver, Receiver and Scoreboard
  • Implementing the coverage model
  • Building the top-level verification environment
  • Defining weighted random, corner case and directed
  • Building the functional and
    code coverage reports

MODULE 15

Business communication

  • Transition from College to Corporate
  • Interpersonal skills and Presentation Skills
  • Email Etiquette
  • Resume writing
  • Interview Skills: Group Discussion and HR Round Preparation
  • Mockup Interviews Technical/HR

Career Support

Maven Silicon offers placement support through a non-commercial placement cell, which taps job opportunities in leading semiconductor companies regularly.

The placement cell at Bangalore maintains a real time cache of information for prospective employers and matches their requirements from its data bank of students, catalogued according to skill sets and merit.

We're dedicated to the success of our trainees. Listen from our CEO Mr. P R Sivakumar, how our powerful training and support services help you reach your goals.

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Why Maven Silicon?

UVM Training Courses

Dynamic
Course structure

ASIC Verification Course

Highly qualified
faculties

SystemVerilog Training

State-of-
art infrastructure

UVM Training Courses

Hands-on
Training

ASIC Verification Course

24*7 Lab
Access & Support

SystemVerilog Training

Continuous
practice tests

UVM Training Courses

Technical group
discussion

ASIC Verification Course

MASS
(24*7 online support)

SystemVerilog Training

1:1 Mentoring

UVM Training Courses

Mock interviews

Admission Process

Recommended Background

BE/BTech in EEE/ECE/TE/CSE/IT/Instrumentation

ME/MTech/MS in Electronics/MSc Electronics

Prerequisite - Completion of VLSI Design Methodologies Course | Good knowledge of Verilog

Fill the application form

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Online Entrance Test

Candidates will be short listed for the online entrance test based on their qualification and academic performance. Short listed candidates will be intimated with the details of online test.

Technical Interview

Candidates who clear the online test will have an interview round with the technical interview panel. Once candidate clears this round, he/she is eligible to register for the course

Scholarship Details

There are two options to avail scholarship for Advanced ASIC Verification Course.

Option1 – Scholarship upto 100%

Step 1: Subscribe online VLSI Design Methodologies at  https://elearn.maven-silicon.com/vlsi-design-course. with the special offer of 30% discount. You can apply the coupon code MSOFF30 on course fee  to avail this Limited period special offer.

Step 2: Complete the online VLSI Design Methodologies with Good Grade

Step 3: Attend Technical and HR interview to avail upto 100% Scholarship

Option2 – Scholarship upto 20%

  • Scholarship will be provided based on criteria mentioned below and telephonic interview
  • Candidates with score 60% and above will be selected for the course.
Scholarship
Scheme		Academic Criteria
[Degree,12th & 10th]		Maven sillicon
online test score		Scholarship on
course fee
MS170% & above80% & aboveUpto 20%
MS260% & above70% & aboveUpto 10%

Batch Calendar

July 07th
2021

Aug 04th
2021

Sep 08th
2021

Payments

Candidates can pay the Course fees through

Net Banking

Credit/Debit
Card

Cheque, DD

Enquire

  • Call Us

    +91 91084 90555

  • Mail Us

    vlsivm@maven-silicon.com

  • Whatsapp Us

    +91 90360 55100

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