Physical Design Flow
In this article, let me explain the full custom design flow which involves the physical design of transistors of the circuit and the interconnectivity between these transistors. Physical Design is a ...
Category: Verification
Clock Domain Crossing
Today’s device needs multiple clocks with increasing system integration, peripherals & external interfaces, and power management. In a design with multiple clocks, clock domain crossing occurs when...
SoC Verification Flow and Methodologies
We need more and more complex chips and SoCs for all new applications that use the latest technologies like AI. For example, Apple’s 5nm SoC A14 features 6-core CPU, 4 core-GPU and 16-core neural e...
RISC VS CISC
RISC is a Reduced Instruction Set Computer. We prefer RISC primarily for battery-operated
light-weight applications like IoT devices that use embedded system controllers or mobile
phones that.
SystemVerilog – Class based Verification environment
This video explains why we prefer Object Oriented Programming to create the class-based verification environment in SystemVerilog...
Verification IP Vs Testbench
Anyone can create a testbench and verify the design, but it can’t be simply reused as a verification IP. Most of the module/IP level testbenches are used once to verify the design. We always want t...
Code Coverage
Though we use both code and functional coverage to sign-off the design verification, they are not the same. So, you need to understand what is code coverage and how it is used to improve the quality.
Is it worth learning SystemVerilog in college itself?
It’s definitely worth it, but not mandatory to get into the semiconductor industry. SystemVerilog is the most preferred language for the IP & Sub-system verification that demands constrained.
How do I get a job in ASIC/FPGA verification?
As a verification engineer, you should be good at finding bugs in the design and disproving the designer, while verifying and proving the design [DUT/DUV] functionality as per.
SystemVerilog OOP – Polymorphism
This video explains how we use Object Oriented Programming feature Polymorphism to create SystemVerilog testbench which can generate various random test scenarios to verify the RTL.
