When Verification Leads
We electronics engineers always assume that the verification is a secondary process like software testing, but in chip design process the verification is critical and it’s going to even lead th...
Category: Verification
Reusable SystemVerilog Testbench
Explains the need and concept of a configurable testbench. Also it explains how we implement the reusable testbench and testcases in SystemVerilog language. More importantly, how we generate differen...
Verification Process
Explains the complete verification process. How we verification engineers start off with the verification plan, create testbench and testcases in SystemVerilog , and then finally how we automate the ...
