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Category: Verification

ASIC Verification Trends

May 8, 2020May 15, 2020 Sivakumar P R
The industry uses majorly three kinds of verification technologies: Dynamic Verification – Simulation
Blog Verification 

SystemVerilog Testbench/Verification Environment Architecture

May 7, 2020May 15, 2020 Sivakumar P R
Most of the well-known SystemVerilog textbooks available in the market explain the language concepts focusing more on language constructs, keywords, datatypes, examples, etc., without following a pro...
Blog Verification 

Functional Coverage

May 6, 2020May 15, 2020 Sivakumar P R
In this article, let us see how functional coverage is different from code coverage and how do we use it to sign-off the.
Blog Verification 

SystemVerilog Interfaces

May 4, 2020May 15, 2020 Sivakumar P R
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This video explains why we prefer SystemVerilog interfaces than Verilog port level connections to build the IPs & Chips. It also explains the difference between Verilog port level connection and Syst...
Verification Videos 

Test Plan Vs Verification Plan[Vplan]

April 24, 2020May 15, 2020 Sivakumar P R
Test Plan is a traditional term primarily used for the directed test cases that we used to create in HDL - Verilog/VHDL. But in SystemVerilog [SV], we create random test cases, as the language suppor...
Blog Verification 

Why do we prefer Packets/Transactions to create SV TB as a TLM?

April 24, 2020May 15, 2020 Sivakumar P R
In SystemVerilog, you can define the transaction[packet/frame] using class data type. But you should know why we prefer transactions to implement SV TB as a TLM[Transaction].
Blog Verification 

How do I learn SystemVerilog in a week?

April 14, 2020May 16, 2020 Sivakumar P R
You can learn and get some exposure, but becoming an expert user of SystemVerilog[SV] depends on your prior programming experience in Verilog and any OOP based languages like++.
Blog Verification 

Is it worth reading SystemVerilog LRM?

April 3, 2020May 16, 2020 Sivakumar P R
Language Reference Manual is the main source of reference for everyone, EDA vendor, Design & Verification Engineer, Training,.
Blog Verification 

Which protocols are good for a fresh VLSI verification engineer to get a job?

April 3, 2020May 16, 2020 Sivakumar P R
Mostly we use AMBA bus protocols AXI/AHB for the on-chip bus [backplane] communication in any SoC. So, learning AMBA protocols will be a.
Blog Verification 

PSS – Portable Test and Stimulus Standard

March 24, 2020May 16, 2020 Sivakumar P R
Every aspiring and growing verification engineer might be searching for the answer to the question ‘What is PSS?’, as it’s an interesting concept that will transform the manual or semi-automate...
Blog Verification 

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Maven Silicon
  • Home
  • About Us
    • About Us
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    • Why Maven Silicon?
  • Blog
  • Admissions
    • Application
    • Training Calendar
    • Online Test
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    • Job Oriented Course
      • Advanced VLSI Design and Verification Course – [VLSI RN]
      • Blended Learning VLSI Program – [Blended VLSI RN]
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