UVM SoC Testbench
This video explains how we reuse the IP level UVM test benches at the SoC [System on Chip] level, reusing the IP level UVM sequences to generate various SoC level.
Category: Verification
How can we model a transaction for the Scoreboard?
We define the transaction mainly based on the DUT [Design Under Test - RTL design] interface for the complete testbench infrastructure[Verification Environment], irrespective of.
How do you verify your DUT thoroughly?
It’s not simple as you always assume and misguide others saying, ‘all you need is a great coding skill to write a testbench in SystemVerilog or UVM and the verification job’.
ASIC Verification Trends
The industry uses majorly three kinds of verification technologies:
Dynamic Verification – Simulation
SystemVerilog Testbench/Verification Environment Architecture
Most of the well-known SystemVerilog textbooks available in the market explain the language concepts focusing more on language constructs, keywords, datatypes, examples, etc., without following a pro...
Functional Coverage
In this article, let us see how functional coverage is different from code coverage and how do we use it to sign-off the.
SystemVerilog Interfaces
This video explains why we prefer SystemVerilog interfaces than Verilog port level connections to build the IPs & Chips. It also explains the difference between Verilog port level connection and Syst...
Test Plan Vs Verification Plan[Vplan]
Test Plan is a traditional term primarily used for the directed test cases that we used to create in HDL - Verilog/VHDL. But in SystemVerilog [SV], we create random test cases, as the language suppor...
Why do we prefer Packets/Transactions to create SV TB as a TLM?
In SystemVerilog, you can define the transaction[packet/frame] using class data type. But you should know why we prefer transactions to implement SV TB as a TLM[Transaction].
How do I learn SystemVerilog in a week?
You can learn and get some exposure, but becoming an expert user of SystemVerilog[SV] depends on your prior programming experience in Verilog and any OOP based languages like++.
