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Category: Videos

SystemVerilog – Class based Verification environment

June 17, 2020October 8, 2020 Sivakumar P R
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This video explains why we prefer Object Oriented Programming to create the class-based verification environment in SystemVerilog...
Verification Videos 

SystemVerilog OOP – Polymorphism

June 4, 2020June 5, 2020 Sivakumar P R
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This video explains how we use Object Oriented Programming feature Polymorphism to create SystemVerilog testbench which can generate various random test scenarios to verify the RTL.
Verification Videos 

Create a winning LinkedIn profile

May 18, 2020March 22, 2022 Sweety Dharamdasani
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Did you know? A hire is made every 10 seconds using LinkedIn. Fact from LinkedIn.
Videos VLSI Training 

UVM SoC Testbench

May 15, 2020June 17, 2020 Sivakumar P R
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This video explains how we reuse the IP level UVM test benches at the SoC [System on Chip] level, reusing the IP level UVM sequences to generate various SoC level.
Verification Videos 

How to ace a Group Discussion

May 14, 2020May 15, 2020 Sweety Dharamdasani
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Group Discussion!  I’m sure all of you must have heard or been a part of this activity as part of your job interview process. Some of us also really look forward to escaping it or pray for a...
Videos VLSI Training 

SystemVerilog Interfaces

May 4, 2020May 15, 2020 Sivakumar P R
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This video explains why we prefer SystemVerilog interfaces than Verilog port level connections to build the IPs & Chips. It also explains the difference between Verilog port level connection and Syst...
Verification Videos 

How To Be A Charming Communicator

April 2, 2020May 16, 2020 Sweety Dharamdasani
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Communication! Isn’t it the most important skill in your workplace? From meeting rooms to cafeterias, from initial interview to final exits, from brainstorming to putting minutes of meeting t...
Videos VLSI Training 

Verilog Programming Series – Finite State Machine

December 16, 2019May 16, 2020 Sivakumar P R
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This video explains how to write a synthesizable Verilog program for a simple sequence detector, following the FSM coding style in Verilog. In this video blogging series, we will be explaining the Ve...
Verilog HDL Videos 

Verilog Programming Series – Dual Port Synchronous RAM

December 9, 2019May 16, 2020 Sivakumar P R
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This video explains how to write a synthesizable Verilog program for Dual Port Synchronous RAM, using Verilog parameters. In this video blogging series, we will be explaining the Verilog coding style...
Verilog HDL Videos 

Verilog Programming Series – Modulo-12 Counter

November 29, 2019May 16, 2020 Sivakumar P R
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This video explains how to write a synthesizable Verilog program for Modulo-12 loadable counter and how to define the priorities of various control signals. In this video blogging series, we will be ...
Verilog HDL Videos 

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Maven Silicon
  • Home
  • About Us
    • About Us
    • CEO’s message
    • Partners
    • Why Maven Silicon?
  • Blog
  • Admissions
    • Application
    • Training Calendar
    • Online Test
  • Program Offerings
    • Job Oriented Course
      • Advanced VLSI Design and Verification Course – [VLSI RN]
      • Blended Learning VLSI Program – [Blended VLSI RN]
      • Advanced ASIC Verification Course – [VLSI VM]
    • Corporate Training
    • Online VLSI Courses
    • Online VLSI Design Methodologies [ VLSI DM ]
    • VLSI Internship
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      • VLSI Design Course [VLSI DM-PT]
      • Advanced ASIC Verification Course [ VLSI VM-PT ]
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