This video explains how we use Object Oriented Programming feature Polymorphism to create SystemVerilog testbench which can generate various random test scenarios to verify the RTL.
This video explains how we reuse the IP level UVM test benches at the SoC [System on Chip] level, reusing the IP level UVM sequences to generate various SoC level.
Group Discussion!
I’m sure all of you must have heard or been a part of this activity as part of your job interview process.
Some of us also really look forward to escaping it or pray for a...
This video explains why we prefer SystemVerilog interfaces than Verilog port level connections to build the IPs & Chips. It also explains the difference between Verilog port level connection and Syst...
Communication!
Isn’t it the most important skill in your workplace?
From meeting rooms to cafeterias, from initial interview to final exits, from brainstorming to putting minutes of meeting t...
This video explains how to write a synthesizable Verilog program for a simple sequence detector, following the FSM coding style in Verilog. In this video blogging series, we will be explaining the Ve...
This video explains how to write a synthesizable Verilog program for Dual Port Synchronous RAM, using Verilog parameters. In this video blogging series, we will be explaining the Verilog coding style...
This video explains how to write a synthesizable Verilog program for Modulo-12 loadable counter and how to define the priorities of various control signals. In this video blogging series, we will be ...