Corporate Training VLSI Courses

Tailor-made VLSI Training for your Workforce

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Corporate Training VLSI Courses

Maven Silicon offers corporate training VLSI courses that deliver highly engaging, immersive learning experiences that ensure learning agility. Our design and verification consultants train your engineers on the advanced design and verification methodologies with outcome-based learning. This program is specially designed for engineers keeping in view the ever changing demands of industry. The participants are equipped with the latest EDA tools, techniques and skills needed to excel as Verification Engineers.

Maven Silicon specializes in tailor made VLSI training courses for corporates that meet your organizations learning objectives. Some of our Corporate training VLSI Courses are SystemVerilog HVL, Verilog HDL, Universal Verification Methodology and Assertion based Verification. Our training delivery models range from ILT, VILT, Self-Paced Learning to Hybrid Learning.

What makes our Corporate Training courses unique?

Delivered by Industry Experts - Train with courses designed & delivered by highly experienced industry veterans.

Effective learning paths - Training in latest technologies, with a co-created and co-curated curriculum

Learning experience platform - Diverse elements to support hands-on learning

Flexible & Customizable - A mélange of Infrastructure as a service, Platform as a service and Learning as a service.

Online Demo Class

Demo Class gives an overview of Universal Verification Methodology, UVM TB architecture, and Reusable VIP using UVM.

Please fill the below form and click “View Demo” to enjoy the online session

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Instructions

You can apply for the demo class only one time.

Your mobile will receive the OTP.

Use the OTP to view the demo class anytime within 24 Hrs.

If you find any trouble in watching demo class videos,

contact us at corporate@maven-silicon.com

  • Call Us

    +91 9036055100

  • Mail Us

    admission@maven-silicon.com

Course Library

SYSTEMVERILOG HVL | 5 DAYS

ASIC Verification Methodologies
  • Directed Vs Random
  • Functional verification process
  • Stimulus Generation
  • Bus function model
  • Monitors and reference models
  • Coverage Driven Verification
  • Verification Planning and management

SystemVeilog HVL

Introduction to System Verilog
  • New Data types
  • Tasks and Functions
  • Interfaces
  • Clocking block
Object Oriented Programming and Randomization
  • OOP Basics
  • Classes - Objects and handles
  • Randomization
  • Constraints
Threads and Virtual Interfaces
  • Fork Join
  • Fork Join_any
  • Fork Join_none
  • Event controls
  • Mailboxes and semaphores
  • Virtual Interfaces
  • Transactors
  • Building verification environment
  • Testcases
Callbacks
  • Facade Class
  • Building Reusable Transactors
  • Inserting Callbacks
  • Registering Callbacks
Direct Programming Interface
  • Coverage mdels
  • Coverpoints and bins
  • Cross coverage
  • Regression testing
Advanced System Verilog
  • Environment Configuration
  • Referene Models and Predictor Logics
  • Using Legacy BFMs
  • Scenario Generation
  • Testcases - Random, Directed and Corner Case
  • Corner Case
Verification Planning and Management
  • Verification Plan
  • TB Architecture
  • Coverage Model
  • Tracking the simulation process
  • Building regression testsuite
  • Testsuite optimiation

VERILOG HDL | Duration : 5 Days

Verilog HDL - RTL Coding and Synthesis
Introduction to Verilog HDL
  • Application of Verilog HDL
  • Verilog HDL language concepts
  • Verilog language basics and constructs
  • Abstraction levels
Data Types
  • Type concept
  • Nets and registers
  • Non hardware equivalent variables
  • Arrays
Verilog Operators
  • Logical operators
  • Bitwise and Reduction operators
  • Concatenation and conditional
  • Relational and arithmetic
  • Shift and Equality operators
  • Operators precedence
Assignments
  • Types of assignments
  • Continuous assignments
  • Timing references
  • Procedures
  • Blocking and Non-Blocking assignments
  • Execution branching
  • Tasks and Functions
Finite State Machine
  • Basic FSM structure
  • Moore Vs Mealy
  • Common FSM coding styles
  • Registered outputs
Advanced Verilog for Verification
  • System Tasks
  • Internal variable monitoring
  • Compiler directives
  • File input and output
Synthesis Coding Style
  • Registers in Verilog
  • Unwanted Latches
  • Operator synthesis
  • RTL Coding Style
Code Coverage
  • Statement coverage
  • Branch Coverage
  • Expression Coverage
  • Path Coverage
  • Toggle Coverage
  • FSM - State, Arc and Sequence overage

UNIVERSAL VERIFICATION METHODOLOGY - [UVM] | 5 DAYS

Introduction to UVM Methodology
  • Overview of Project
  • UVM TB Architecture
  • Stimulus Modeling
  • Creating UVCs and Environment
  • UVM Simulation Phases
  • Testcase Classes
  • TLM Overview
  • Configuring TB Environment
  • UVM Sequences
  • UVM sequencers
  • Connecting DUT - Virtual Interface
  • Virtual Sequenes and Sequencers
  • Creating TB Infrastructure
  • Connecting multiple UVCs
  • Building a Scoreboard
  • Introduction to Register Modeling
  • Building reusable environments

What our customers say?

Enquiry Form

FAQ

How can we plan the training?

You can fill up the enquiry form. Our team will schedule a call with you to discuss your requirements and help you choose the right solution.

Do you provide corporate training in advanced VLSI concepts?

Maven Silicon offers customized inhouse and onsite corporate VLSI training courses. This program is specially designed for engineers keeping in view the ever-changing demands of industry. The participants are equipped with the latest tools, techniques and skills needed to excel as Verification Engineers. Some of our Corporate training VLSI Courses are SystemVerilog HVL, Verilog HDL, Universal Verification Methodology and Assertion based Verification. Click here for more details: https://www.maven-silicon.com/corporate-training

What is the corporate training course duration?

The duration of Corporate training courses vary basis the modules and delivery format you choose. Some of our Corporate training VLSI Courses are SystemVerilog HVL, Verilog HDL, Universal Verification Methodology and Assertion based Verification. You can choose ILT (Instructor Led Training), VILT (Virtual Instructor Led Training), Online or Hybrid format. The duration for our regular ILT courses is i.e. SystemVerilog - 5 days, Verilog - 5 Days, UVM - 5 days

Is there any online course available for corporate training?

Yes. We do have online courses for corporate training. Fill up the enquiry form or call at 91 9148372555 to speak to our corporate training manager for details.

Can I take up the training as an individual or it is necessary to be a part of group/organization?

If you want to upskill yourself individually, please browse through our program offering section. We have Part time Advanced ASIC Verification Course which you can continue along with your job and enhance your VLSI skills.

Who would be the trainer?

The trainers are highly qualified and experienced Industry experts with great expertise in delivering the SystemVerilog training courses and UVM training courses.

What would be the premises for training?

You have the option to choose whether you want an onsite or offsite training.

Do you offer Corporate training outside Bangalore?

Yes. We regularly conduct corporate training sessions in Hyderabad, Noida, New Delhi, Chennai etc.