VLSI Training for Corporate Employees - Maven Silicon

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Corporate Training Topics

RTL Verification

Testing & Timing

Physical Design & Verification

RTL Design Course
This course covers all the topics like Advanced Digital Design, Verilog HDL, RTL Synthesis Using DC Compiler, RTL Linting using Spyglass, System Verilog for Design, Equivalence Checking using Formality, Static Timing Analysis using PrimeTime, Learning FPGA using Xilinx Vivado ML, Gate Level Simulation (GLS), Clock Domain Crossing
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RTL Design Course — RTL Design Course
This course covers all the topics like Advanced Digital Design, Verilog HDL, RTL Synthesis Using DC Compiler, RTL Linting using Spyglass, System Verilog for Design, Equivalence Checking using Formality, Static Timing Analysis using PrimeTime, Learning FPGA using Xilinx Vivado ML, Gate Level Simulation (GLS), Clock Domain Crossing
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Advanced Digital Design
This advanced Digital Design course covers the complete digital design and static timing analysis. The Digital module explains the concepts of combinational, sequential, FSM logic designs and Memories. It is composed of modules which explain the concepts of Logic Gates, Adders, Subtractors, Decoder, Encoders, Multiplexer, Demultiplexer, Flipflops, Latches, Counters, Registers, Memories and Finite state machines. Also, the STA module explains the importance of timing analysis, how to do the timing analysis on both combinational Logic Circuits and Sequential Circuits and the different strategies that one can implement to improve the speed of the logic circuits.
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Advanced Digital Design — Advanced Digital Design
This advanced Digital Design course covers the complete digital design and static timing analysis. The Digital module explains the concepts of combinational, sequential, FSM logic designs and Memories. It is composed of modules which explain the concepts of Logic Gates, Adders, Subtractors, Decoder, Encoders, Multiplexer, Demultiplexer, Flipflops, Latches, Counters, Registers, Memories and Finite state machines. Also, the STA module explains the importance of timing analysis, how to do the timing analysis on both combinational Logic Circuits and Sequential Circuits and the different strategies that one can implement to improve the speed of the logic circuits.
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Verilog HDL
This hands-on Verilog course covers coding for synthesis and simulation. It explains the concept of hardware description language and basic concepts like data types and operators. Then it explains advanced concepts like assignments, procedural blocks, synthesis coding style, FSM coding, and self-checking testbench coding. This course is composed of theory modules, quizzes, labs, and pilot projects. It trains you extensively on Verilog HDL programming using various lab exercises and a pilot Verilog RTL project and makes you a hands-on Verilog RTL designer.
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Verilog HDL — Verilog HDL
This hands-on Verilog course covers coding for synthesis and simulation. It explains the concept of hardware description language and basic concepts like data types and operators. Then it explains advanced concepts like assignments, procedural blocks, synthesis coding style, FSM coding, and self-checking testbench coding. This course is composed of theory modules, quizzes, labs, and pilot projects. It trains you extensively on Verilog HDL programming using various lab exercises and a pilot Verilog RTL project and makes you a hands-on Verilog RTL designer.
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RTL Synthesis Using DC Compiler
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RTL Synthesis Using DC Compiler — RTL Synthesis Using DC Compiler
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RTL Linting using Spyglass
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RTL Linting using Spyglass — RTL Linting using Spyglass
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System Verilog for Design
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System Verilog for Design — System Verilog for Design
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Equivalence Checking using Formality
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Equivalence Checking using Formality — Equivalence Checking using Formality
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Static Timing Analysis using PrimeTime
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Static Timing Analysis using PrimeTime — Static Timing Analysis using PrimeTime
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Learning FPGA using Xilinx Vivado ML
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Learning FPGA using Xilinx Vivado ML — Learning FPGA using Xilinx Vivado ML
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Gate Level Simulation (GLS)
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Gate Level Simulation (GLS) — Gate Level Simulation (GLS)
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Clock Domain Crossing
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Clock Domain Crossing — Clock Domain Crossing
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RTL Verification Course
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RTL Verification Course — RTL Verification Course
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SystemVerilog for Verification Theory & Labs
This hands-on SystemVerilog course explains all the language data types and concepts, especially how we can use all the language features to create a class-based verification environment. It explains all the data types, language features like interfaces, OOP, randomisation, functional coverage, and verification planning and management, and testbench architecture, in detail, and trains you extensively on creating the class-based verification environment using various lab exercises and real-time IP and SoC case studies.
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SystemVerilog for Verification Theory & Labs — SystemVerilog for Verification Theory & Labs
This hands-on SystemVerilog course explains all the language data types and concepts, especially how we can use all the language features to create a class-based verification environment. It explains all the data types, language features like interfaces, OOP, randomisation, functional coverage, and verification planning and management, and testbench architecture, in detail, and trains you extensively on creating the class-based verification environment using various lab exercises and real-time IP and SoC case studies.
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Universal Verification Methodology ( UVM ) Theory & Labs
This UVM hands-on course begins with a good overview of UVM methodology, explaining the concepts like agents and UVCs with various examples like AHB UVCs and SOC UVM test benches. With this overview, walks you through all the concepts like UVM TB framework, base class library, factory, sequences, phases, reporting mechanism, TLM ports, virtual sequences, events, callbacks, UVCs, Scoreboard, UVM environment, etc and guides you to do the lab exercises to understand all the concepts very well. Also, this course explains the need and usage of UVM with real-time case studies, IP and SoC UVM TBs. With the help of this hands-on course, one can learn the nuts and bolts of UVM and grow as a UVM expert in the functional verification domain.
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Universal Verification Methodology ( UVM ) Theory & Labs — Universal Verification Methodology ( UVM ) Theory & Labs
This UVM hands-on course begins with a good overview of UVM methodology, explaining the concepts like agents and UVCs with various examples like AHB UVCs and SOC UVM test benches. With this overview, walks you through all the concepts like UVM TB framework, base class library, factory, sequences, phases, reporting mechanism, TLM ports, virtual sequences, events, callbacks, UVCs, Scoreboard, UVM environment, etc and guides you to do the lab exercises to understand all the concepts very well. Also, this course explains the need and usage of UVM with real-time case studies, IP and SoC UVM TBs. With the help of this hands-on course, one can learn the nuts and bolts of UVM and grow as a UVM expert in the functional verification domain.
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Assertion-based Verification
This Assertion Based Verification [ SVA ] hands-on course explains the concept of Assertion Based Verification [ ABV ] using SystemVerilog assertions [ SVA ] and how one can verify the DUT protocol or functionality using the same. As part of the course, we will walk you through all the concepts like immediate and concurrent assertions, sequences, implication & repetition operators, writing complex assertions using sequences, etc. and guide you to do all the necessary labs to understand the same. We use assertions primarily to verify the DUT protocol and functionality. Also, assertions are very powerful in debugging the simulation failures efficiently and verifying the DUT functionality through formal verification technologies too.
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Assertion-based Verification — Assertion-based Verification
This Assertion Based Verification [ SVA ] hands-on course explains the concept of Assertion Based Verification [ ABV ] using SystemVerilog assertions [ SVA ] and how one can verify the DUT protocol or functionality using the same. As part of the course, we will walk you through all the concepts like immediate and concurrent assertions, sequences, implication & repetition operators, writing complex assertions using sequences, etc. and guide you to do all the necessary labs to understand the same. We use assertions primarily to verify the DUT protocol and functionality. Also, assertions are very powerful in debugging the simulation failures efficiently and verifying the DUT functionality through formal verification technologies too.
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Simulation Debugging using Verdi
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Simulation Debugging using Verdi — Simulation Debugging using Verdi
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SoC Verification Flow
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SoC Verification Flow — SoC Verification Flow
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Formal Verification using Formality
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Formal Verification using Formality — Formal Verification using Formality
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Low Power Verification using UPF
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Low Power Verification using UPF — Low Power Verification using UPF
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Gate Level Simulation ( GLS) on RISC V
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Gate Level Simulation ( GLS) on RISC V — Gate Level Simulation ( GLS) on RISC V
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Testing & Timing Course
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Testing & Timing Course — Testing & Timing Course
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Static Timing Analysis using PrimeTime
Static Timing Analysis is one of the important processes in ASIC design flow. By performing Static Timing Analysis, the designer can ensure that the design is meeting the timing requirements and it is working at the required clock frequency without setup and hold time violations. In this course, you will be able to understand the importance of timing analysis, how to do the timing analysis on both combinational Logic Circuits and Sequential Circuits and the different strategies that you can implement to improve the speed of the logic circuits. This course will help you to understand the concepts of STA from a very basic level and gradually take you to an advanced level.
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Static Timing Analysis using PrimeTime — Static Timing Analysis using PrimeTime
Static Timing Analysis is one of the important processes in ASIC design flow. By performing Static Timing Analysis, the designer can ensure that the design is meeting the timing requirements and it is working at the required clock frequency without setup and hold time violations. In this course, you will be able to understand the importance of timing analysis, how to do the timing analysis on both combinational Logic Circuits and Sequential Circuits and the different strategies that you can implement to improve the speed of the logic circuits. This course will help you to understand the concepts of STA from a very basic level and gradually take you to an advanced level.
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Clock Domain Crossing
In a Chip/IP with multiple clocks, clock domain crossing occurs whenever data is transferred from a flip-flop driven by one clock to a flip-flop driven by another clock. CDC Signals originate in one clock domain and are sampled by registers in a different clock domain. Today’s System on Chip needs multiple clocks with increasing system integration, increasing peripherals & external interfaces and for power management. This CDC module explains what is Clock Domain Crossing, how to avoid metastability, different kinds of synchronisers and CDC analysis.
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Clock Domain Crossing — Clock Domain Crossing
In a Chip/IP with multiple clocks, clock domain crossing occurs whenever data is transferred from a flip-flop driven by one clock to a flip-flop driven by another clock. CDC Signals originate in one clock domain and are sampled by registers in a different clock domain. Today’s System on Chip needs multiple clocks with increasing system integration, increasing peripherals & external interfaces and for power management. This CDC module explains what is Clock Domain Crossing, how to avoid metastability, different kinds of synchronisers and CDC analysis.
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RTL Linting using Spyglass
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RTL Linting using Spyglass — RTL Linting using Spyglass
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RTL Synthesis Using DC Compiler
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RTL Synthesis Using DC Compiler — RTL Synthesis Using DC Compiler
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Design for testability - DFT
Design For Testability is one of the essential processes in VLSI Design Flow. It is intended to detect the manufacturing defects in a fabricated chip since the fabrication process's yield is never 100%. DFT methodology offers various techniques to increase the efficiency of the silicon testing process of a fabricated chip. This DFT Training course will cover the necessary basics of silicon testing, the importance of testing, and different DFT techniques such as SCAN Insertion, ATPG, JTAG, and BIST. Also, this course will give the learners a hands-on experience of the implementation of all DFT techniques using the industry-standard tool Tessent from Mentor Graphics. Any Electronics Engineer with a good knowledge of Digital Electronics, RTL Design using Verilog HDL, and moderate programming skills can learn DFT concepts from this course and grow as a DFT Engineer.
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Design for testability - DFT — Design for testability - DFT
Design For Testability is one of the essential processes in VLSI Design Flow. It is intended to detect the manufacturing defects in a fabricated chip since the fabrication process's yield is never 100%. DFT methodology offers various techniques to increase the efficiency of the silicon testing process of a fabricated chip. This DFT Training course will cover the necessary basics of silicon testing, the importance of testing, and different DFT techniques such as SCAN Insertion, ATPG, JTAG, and BIST. Also, this course will give the learners a hands-on experience of the implementation of all DFT techniques using the industry-standard tool Tessent from Mentor Graphics. Any Electronics Engineer with a good knowledge of Digital Electronics, RTL Design using Verilog HDL, and moderate programming skills can learn DFT concepts from this course and grow as a DFT Engineer.
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LBIST & MBIST
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LBIST & MBIST — LBIST & MBIST
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Physical Design & Verification Course
This course covers all the topics like RTL Linting & Design Optimization using Fusion Compiler, Static Timing Analysis using PrimeTime, Physical Design using Synopsys ICC2 or Fusion Compiler, Physical Verification & Sign off using Siemens Calibre
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Physical Design & Verification Course — Physical Design & Verification Course
This course covers all the topics like RTL Linting & Design Optimization using Fusion Compiler, Static Timing Analysis using PrimeTime, Physical Design using Synopsys ICC2 or Fusion Compiler, Physical Verification & Sign off using Siemens Calibre
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RTL Linting & Design Optimization using Fusion Compiler
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RTL Linting & Design Optimization using Fusion Compiler — RTL Linting & Design Optimization using Fusion Compiler
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Static Timing Analysis using PrimeTime
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Static Timing Analysis using PrimeTime — Static Timing Analysis using PrimeTime
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Physical Design using Synopsys ICC2 or Fusion Compiler
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Physical Design using Synopsys ICC2 or Fusion Compiler — Physical Design using Synopsys ICC2 or Fusion Compiler
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Physical Verification & Sign off using Siemens Calibre
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Physical Verification & Sign off using Siemens Calibre — Physical Verification & Sign off using Siemens Calibre
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RISC-V Advanced Program
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RISC-V Advanced Program — RISC-V Advanced Program
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RISC-V RV32I RTL Design using Verilog HDL
This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to implement the RTL design using Verilog HDL. As part of this training you will be trained extensively on Verilog HDL RTL, how you can use the language features for RTL synthesis and simulation, using various lab exercises. Finally, you will implement the RTL design of a pipeline RISC-V processor in Verilog HDL, following best design and verification practices, and coding styles.
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RISC-V RV32I RTL Design using Verilog HDL — RISC-V RV32I RTL Design using Verilog HDL
This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to implement the RTL design using Verilog HDL. As part of this training you will be trained extensively on Verilog HDL RTL, how you can use the language features for RTL synthesis and simulation, using various lab exercises. Finally, you will implement the RTL design of a pipeline RISC-V processor in Verilog HDL, following best design and verification practices, and coding styles.
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RISC-V RV32I RTL Verification using UVM
This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to verify the RISC-V Verilog RTL design using UVM. As part of this training you will be trained extensively on UVM, how you can use the language and UVM methodology features for the RTL verification, using various lab exercises and IP and SoC case studies. Finally, you will implement a UVM class-based verification environment and verify the pipeline RISC-V processor RTL design implemented in Verilog HDL, following best verification practices and coding styles.
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RISC-V RV32I RTL Verification using UVM — RISC-V RV32I RTL Verification using UVM
This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to verify the RISC-V Verilog RTL design using UVM. As part of this training you will be trained extensively on UVM, how you can use the language and UVM methodology features for the RTL verification, using various lab exercises and IP and SoC case studies. Finally, you will implement a UVM class-based verification environment and verify the pipeline RISC-V processor RTL design implemented in Verilog HDL, following best verification practices and coding styles.
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RISC-V RTL Design
This RISC-V RTL Design course explains the complete RTL design process, how you can create a basic architecture for J-type instructions initially and scale up the same sequentially in phases to implement all other RV 32 I instructions. In this course, you will explore how you can create a processor using all the basic building blocks like register, memory, adder, multiplexer, ALU, decoder and control logic like FSMs. Also, it explains why CPU performance is very essential and how to improve CPU performance through a pipeline design methodology. In this course, you will explore how to implement a five-stage pipelined RISC-V processor.
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RISC-V RTL Design — RISC-V RTL Design
This RISC-V RTL Design course explains the complete RTL design process, how you can create a basic architecture for J-type instructions initially and scale up the same sequentially in phases to implement all other RV 32 I instructions. In this course, you will explore how you can create a processor using all the basic building blocks like register, memory, adder, multiplexer, ALU, decoder and control logic like FSMs. Also, it explains why CPU performance is very essential and how to improve CPU performance through a pipeline design methodology. In this course, you will explore how to implement a five-stage pipelined RISC-V processor.
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RISC-V instruction set architecture
This RISC-V ISA course explains RISC-V Instruction Set Architecture and all RV 32 I Instructions in detail with various examples. It begins with explaining the need for a processor and how we create various electronic products using different kinds of chips like embedded micro-controllers and complex SoCs that can be built using a RISC-V processor. In addition to this good overview of the RISC-V processor, it will explain RISC-V ISA and walk you through all RV 32 I instructions. Finally, it will explain RISC-V assembly programming with various examples and make you ready for the RISC-V processor RTL design.
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RISC-V instruction set architecture — RISC-V instruction set architecture
This RISC-V ISA course explains RISC-V Instruction Set Architecture and all RV 32 I Instructions in detail with various examples. It begins with explaining the need for a processor and how we create various electronic products using different kinds of chips like embedded micro-controllers and complex SoCs that can be built using a RISC-V processor. In addition to this good overview of the RISC-V processor, it will explain RISC-V ISA and walk you through all RV 32 I instructions. Finally, it will explain RISC-V assembly programming with various examples and make you ready for the RISC-V processor RTL design.
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ARM Cortex A - V8 - Software Development
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ARM Cortex A - V8 - Software Development — ARM Cortex A - V8 - Software Development
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ARM Cortex A - V7 - Software Development
ARM V7 architecture is the basis for all the current 32-bit ARM Cortex Processors such as Cortx -A9 and A15 processors. This course will cover the features, ISA, memory Mapping, and exception handling in ARMV7 architectures
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ARM Cortex A - V7 - Software Development — ARM Cortex A - V7 - Software Development
ARM V7 architecture is the basis for all the current 32-bit ARM Cortex Processors such as Cortx -A9 and A15 processors. This course will cover the features, ISA, memory Mapping, and exception handling in ARMV7 architectures
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AMBA
Most of the modern-day SoCs are built with ARM cores and several IPs from different IP developers such as SONY, Broadcomm, and Cypress. Integration of several IPs and ARM Cores is done with different AMBA Interfaces. So, AMBA Protocols like AX, AHB and APB are very widely used protocols in modern-day SoCs. This course will help you to understand basic to detailed concepts of AMBA protocols.
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AMBA — AMBA
Most of the modern-day SoCs are built with ARM cores and several IPs from different IP developers such as SONY, Broadcomm, and Cypress. Integration of several IPs and ARM Cores is done with different AMBA Interfaces. So, AMBA Protocols like AX, AHB and APB are very widely used protocols in modern-day SoCs. This course will help you to understand basic to detailed concepts of AMBA protocols.
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Corporate Training Methods

At Maven Silicon, we collaborate with you to determine your desired employee performance and help combine it with our effective learning tracks and right delivery system . We always use the most suitable training method as per your needs to excite, engage and educate your workforce.

Best VLSI Corporate Training Solutions - Maven Silicon

Offline Instructor-Led

Virtual Instructor for Corporate Training

Virtual Live Instructor-Led

Best VLSI Corporate Training Solutions - Maven Silicon

Self-paced

VLSI Hybrid Corporate Training Solutions - Maven Silicon

Blended/Hybrid

Corporate Training Process

1

Discovering Business Objective

Discovering Business Objective

2

Induction to the Trainees

Induction to the Trainees

3

Structured & Flexible Day

Structured & Flexible Day Planners

4

Learning Video Access

Learning Videos Access

5

Lab Access 24x7

24/7 Labs Access

6

Continuous Assessments

Continuous Assessments

7

Reference Materials

Reference Material and Guidance

8

Labs 1:1 reviews

Labs 1:1 reviews

9

Project Source code reviews

Project Source Code Reviews

10

Final Assessments

Final Assessments

11

Specialized Business

Specialized Business Communication sessions

12

Performance Reports

360-degree Performance Reports

13

Detailed Insights For Right Skill Fitment For Projects

Detailed insights for right skill fitment for projects

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