Advanced ASIC Verification Course

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SystemVerilog Online Course

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SystemVerilog Course

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What is VLSI VM-PT?

The Advanced ASIC verification part time course [VLSI VM-PT] trains the working professionals extensively on the Verification methodologies and help them to upgrade their skills and job as ASIC Verification Engineer. The key features of the ASIC Verification course are ASIC Verification Methodologies, Advanced Verilog for Verification, SystemVerilog, UVM, Assertion Based Verification - SVA(SystemVerilog Assertions), Verification Planning and Management, Code and Functional Coverage, Perl scripting language and VIP coding style.

12 Weeks (Weekends)

Part time

10 AM – 6 PM

Why join VLSI VM-PT?

Advanced course on ASIC Verification is a flexible program designed around your schedule and built to get you a job or upgrade yourself as a ASIC Verification engineer. The part-time VLSI course offers high-class training on latest verification skills i.e. SystemVerilog, Assertion Based Verification SVA(SystemVerilog Assertions), UVM from Industry perspective and makes you a ready-to-deploy ASIC Verification Engineer.

Key Features

  • ASIC Verification Methodologies
  • Advanced Verilog for Verification
  • SystemVerilog
  • UVM
  • Assertion Based Verification - SVA(SystemVerilog Assertions)
  • Verification Planning and Management
  • Code and Functional Coverage
  • Scripting - Perl
  • Coding styles for VIPs
  • Pilot Project

EDA Tools

  • Mentor Graphics
  • Xilinx
  • Aldec


The dynamic curriculum of Advanced ASIC Verification Course fits perfectly with the career aim of working professionals and helps them to ‘future-proof’ themselves and remain relevant for the rapidly evolving Semiconductor technology space.


Introduction to Linux

  • Components of UNIX system
  • Directory Structure
  • Utilities and Commands
  • Vi Editor


Advanced Verilog for verification

  • Tasks and Functions
  • Delays - Regular, Intra Assignment
    and Inertial Delays
  • Race Conditions
  • File I/O operation
  • TB Constructs
  • Self checking Testbenches


Code Coverage

  • Statement coverage
  • Branch Coverage
  • Expression Coverage
  • Path Coverage
  • Toggle Coverage
  • FSM - State, Arc and Sequence coverage


ASIC Verification Methodologies

  • Directed Vs Random
  • Functional verification process
  • Stimulus Generation
  • Bus function model
  • Monitors and reference models
  • Coverage Driven Verification
  • Verification Planning and management


[1] Introduction to SystemVerilog

  • New Data types
  • Tasks and Functions
  • Interfaces
  • Clocking Blocks

[2] Object Oriented Programming and Randomization

  • OOP Basics
  • Classes - Objects and handles
  • Polymorphism and Inheritance
  • Randomization
  • Constraints

[3] Threads and Virtual Interfaces

  • Fork Join
  • Fork Join_any
  • Fork Join_none
  • Event controls
  • Mailboxes and semaphores
  • Virtual Interfaces
  • Transactors
  • Building verification environment
  • Test cases

[4] Callbacks

  • Facade Class
  • Building Reusable Transactors
  • Inserting Callbacks
  • Registering Callbacks

[5] Direct Programming Interface

[6] Functional Coverage

  • Coverage models
  • Coverpoints and bins
  • Cross coverage
  • Regression testing


Advanced SystemVerilog

  • Environment Configuration
  • Reference Models and Predictor Logics
  • Using Legacy BFMs
  • Scenario Generation
  • Testcases - Random, Directed and
    Corner Case
  • Coding styles for VIP


Verification Planning and Management

  • Verification Plan
  • TB Architecture
  • Coverage Model
  • Tracking the simulation process
  • Building regression testsuite
  • Testsuite optimization


Assertion Based Verification - SVA(SystemVerilog Assertions)

  • Introduction to ABV
  • Immediate Assertions
  • Simple Assertions
  • Sequences
  • Sequence Composition
  • Advanced SVA(SystemVerilog Assertions) Features
  • Assertion Coverage


UVM-Universal verification Methodology

  • Introduction to UVM Methodology
  • Overview of Project
  • UVM TB Architecture
  • Stimulus Modeling
  • Creating UVCs and Environment
  • UVM Simulation Phases
  • Testcase Classes
  • TLM Overview
  • Configuration TB Environment
  • UVM Sequences
  • UVM Sequencers
  • Connecting DUT - Virtual Interface
  • Virtual Sequences and Sequencers
  • Creating TB Infrastructure
  • Connecting multiple UVCs
  • Building a Scoreboard
  • Introduction to Register Modeling
  • Building reusable environments


Design Automation using Scripts Perl

  • Introduction to Perl
  • Functions and Statements
  • Numbers, Strings, and Quotes
  • Comments and Loops


Pilot project - Verification and RTL Sign-off

  • Project Specification Analysis
  • Understanding the architecture
  • Module level implementation and verification
  • Building the top level module


Industry Standard Project

  • Project specification analysis
  • Defining verification plan
  • Creating Testbench architecture
  • Defining Transaction
  • Implementing the transactors - Generator, Driver, Receiver and Scoreboard
  • Implementing the coverage model
  • Building the top-level verification environment
  • Defining weighted random, corner case and directed
  • Building the functional and
    code coverage reports

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Why Maven Silicon?

SystemVerilog Online Course

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1:1 mentoring

Admission Process

Recommended Background

BE/BTech in EEE/ECE/TE/CSE/IT/Instrumentation

ME/MTech/MS in Electronics/MSc Electronics

Prerequisite - Good knowledge of Verilog

Fill the application form


Batch Calendar

Jun 11th

Jul 09th

Aug 13th


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What are the eligibility criteria for this VLSI course?

To be eligible for the VLSI VM course you would need to tick either of the following :

  1. BE/BTech graduate and certified in Online VLSI Design Methodologies course from Maven Silicon. Click the link to explore the online course:
  2. BE/Btech graduate with a minimum of one-year work experience in VLSI Design
  3. BE/Btech/ME/Mtech/MS with very good knowledge in RTL Design and Verilog HDL

What are the prerequisite topics required to join the ASIC Verification Course?

You should know about Digital Electronics and RTL Design using Verilog Coding Concepts to join this VLSI Course. You can also learn these topics through our Online Design Methodologies Program. To explore click on

Course Delivery

What is the mode of delivery for this course?

The mode of delivery is Blended. Blended means the best of both worlds, Online and Offline. Our Blended course lets you learn at the comfort and safety of your house. It is specially designed for the working professional to upskill their VLSI Knowledge. This course offers training on Advanced Verilog, SystemVerilog, Universal Verification Methodology, Assertion based Verification along labs, and pilot projects. There will be Live doubt clarification sessions on weekends and pilot projects can be done through online /offline.

What kind of extra support will be given during the course?

Apart from the classroom training, inhouse lab infrastructure,24/7 Lab access through a VPN, hands-on experience on industry standard projects we also support you for any kind of your queries via Whatsapp group.

Can I do the labs and projects from home?

Yes, you can do the labs and projects from home as we provide 24/7 Lab access through a VPN.

Course Information

What is the duration of the part-time VM course?

The duration of the course is 12 weeks designed around weekend classes. Classes would be on Saturday and Sunday at Maven Silicon campus

How can I manage to take this course along with my current job?

The USP of the VLSI VM part-time course is the weekend classes. This course lets you make the best use of your time to upgrade your skills without interrupting your current job.


When am I supposed to pay the fee?

After your selection for the admission, you are required to block your seat by paying the registration fee in advance. The remaining fee has to be paid on the reporting day of the course.


Can I bring my laptop?

We are equipped with 250+ laptops/computers to support your learning process. Also, we strictly prohibit the use of your personal laptops/storage device in the premises under the copyright and trademark infringement act.


Does the VLSI VM part-time course makes me eligible for placements at Maven Silicon?

To get our placement support you can join our job oriented Advanced ASIC Verification course. Click the link to explore

Skill up-gradation

I am working for 2 years in the VLSI domain but still do not understand many concepts completely. How can I become a pro in ASIC verification?

Maven Silicon can definitely help you to bridge the skill gaps. In part-time ASIC Verification Course, you can learn SystemVerilog, UVM, Assertion Based Verification - SVA(SystemVerilog Assertions), Verification Planning and Management, Code and Functional Coverage, Perl scripting language and VIP coding style with simple theory concepts and continuous practice and implementation of the concepts in Labs. This acquired knowledge will make you a pro at work.

I am already working in VLSI Industry for 2 years. How VLSI VM course can help me?

With increasing complexity of chips, engineers are required to enhance their verification skills to advance their career and increase their productivity. We help you learn SystemVerilog and UVM skills at a very fast pace that take years to master in the workplace using our combination of theory classes, hands-on training sessions, projects and assessments.

Download the detailed curriculum of the course

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