VLSI design online training institute

What is VLSI VM-PT?

The Advanced ASIC verification part time course [VLSI VM-PT] trains the working professionals extensively on the Verification methodologies and help them to upgrade their skills and job as ASIC Verification Engineer. The key features of the ASIC Verification course are ASIC Verification Methodologies, Advanced Verilog for Verification, SystemVerilog, UVM, Assertion Based Verification - SVA, Verification Planning and Management, Code and Functional Coverage, Perl scripting language and VIP coding style.

12 Weeks (Weekends)

Part time

10 AM – 6 PM

Why join VLSI VM-PT?

Advanced course on ASIC Verification is a flexible program designed around your schedule and built to get you a job or upgrade yourself as a ASIC Verification engineer. The part-time VLSI course offers high-class training on latest verification skills i.e. SystemVerilog, Assertion Based Verification SVA, UVM from Industry perspective and makes you a ready-to-deploy ASIC Verification Engineer.

Key Features

ASIC Verification Methodologies
Advanced Verilog for Verification
SystemVerilog
UVM
Assertion Based Verification - SVA
Verification Planning and Management
Code and Functional Coverage
Scripting - Perl
Coding styles for VIPs
Pilot Project

EDA Tools

Mentor Graphics
Xilinx
Aldec

Curriculum

The dynamic curriculum of Advanced ASIC Verification Course fits perfectly with the career aim of working professionals and helps them to ‘future-proof’ themselves and remain relevant for the rapidly evolving Semiconductor technology space.

MODULE 1

Introduction to Linux

Components of UNIX system
Directory Structure
Utilities and Commands
Vi Editor

MODULE 2

Advanced Verilog for verification

Tasks and Functions
Delays - Regular, Intra Assignment
and Inertial Delays
Race Conditions
File I/O operation
TB Constructs
Self checking Testbenches

MODULE 3

Code Coverage

Statement coverage
Branch Coverage
Expression Coverage
Path Coverage
Toggle Coverage
FSM - State, Arc and Sequence coverage

MODULE 4

ASIC Verification Methodologies

Directed Vs Random
Functional verification process
Stimulus Generation
Bus function model
Monitors and reference models
Coverage Driven Verification
Verification Planning and management

MODULE 5

[1] Introduction to System Verilog

New Data types
Tasks and Functions
Interfaces
Clocking Blocks

[2] Object Oriented Programming and Randomization

OOP Basics
Classes - Objects and handles
Polymorphism and Inheritance
Randomization
Constraints

[3] Threads and Virtual Interfaces

Fork Join
Fork Join_any
Fork Join_none
Event controls
Mailboxes and semaphores
Virtual Interfaces
Transactors
Building verification environment
Test cases

[4] Callbacks

Facade Class
Building Reusable Transactors
Inserting Callbacks
Registering Callbacks

[5] Direct Programming Interface

[6] Functional Coverage

Coverage models
Coverpoints and bins
Cross coverage
Regression testing

MODULE 6

Advanced System Verilog

Environment Configuration
Reference Models and Predictor Logics
Using Legacy BFMs
Scenario Generation
Testcases - Random, Directed and
Corner Case
Coding styles for VIP

MODULE 7

Verification Planning and Management

Verification Plan
TB Architecture
Coverage Model
Tracking the simulation process
Building regression testsuite
Testsuite optimization

MODULE 8

Assertion Based Verification - SVA

Introduction to ABV
Immediate Assertions
Simple Assertions
Sequences
Sequence Composition
Advanced SVA Features
Assertion Coverage

MODULE 9

UVM-Universal verification Methodology

Introduction to UVM Methodology
Overview of Project
UVM TB Architecture
Stimulus Modeling
Creating UVCs and Environment
UVM Simulation Phases
Testcase Classes
TLM Overview
Configuration TB Environment
UVM Sequences
UVM Sequencers
Connecting DUT - Virtual Interface
Virtual Sequences and Sequencers
Creating TB Infrastructure
Connecting multiple UVCs
Building a Scoreboard
Introduction to Register Modeling
Building reusable environments

MODULE 10

Design Automation using Scripts Perl

Introduction to Perl
Functions and Statements
Numbers, Strings, and Quotes
Comments and Loops

MODULE 11

Pilot project - Verification and RTL Sign-off

Project Specification Analysis
Understanding the architecture
Module level implementation and verification
Building the top level module

MODULE 12

Industry Standard Project

Project specification analysis
Defining verification plan
Creating Testbench architecture
Defining Transaction
Implementing the transactors - Generator, Driver, Receiver and Scoreboard
Implementing the coverage model
Building the top-level verification environment
Defining weighted random, corner case and directed
Building the functional and
code coverage reports

Alumni Review

Saurabh Kumar joined Qualcomm - shares his journey at Maven Silicon

The projects done during the course is very useful, once you get into the industry. The curriculum has been designed really well and sets you on a correct... Read More

Saurabh Ramesh Jaipurkar joined PerfectVIP - shares his journey at Maven Silicon

My journey from an Asst Prof to Verification Engineer could only get possible with the Industry standard VLSI training from Maven Silicon.

Giradha Meghana joined Synopsys – shares her journey at Maven Silicon

Along with Good course structure and training methods, 24/7 online support, communication sessions, doubt clarification classes are the key highlight... Read More

Nikhil Satish joined ARM

Awesome!!! The entire team is amazing, dedicated and the work culture is top notch.... Proud Mavenite Forever!!!!

Amith Patil joined Mediatech

If you want to get into semiconductor industry, you should join Maven Silicon. The faculty here are experienced and give students in-depth knowledge of the subjects.

Sujay R Kanikraj joined Juntran

Any IT folks interested in changing their domain to VLSI field then I feel Maven must be their top choice. Highly professional trainers and well-organized labs... Read More

Ram Babu joined Qualcomm

I have been trained in Maven-Silicon and I felt its worth to join here. Subjects will be taught by industrial experts and you can get hands on experience since... Read More

Rakesh Kumar joined Wafer Space

At Maven, they teach us from basics like Digitals, Verilog and verification methodologies like UVM. They concentrate on lab sessions more than theory... Read More

Priyanka Hiremath joined Mirafra Technologies

very easy to understand through simple explanations and the course was just the right mix of theory and practical demonstration. I have gained the... Read More

Saurabh Kumar joined Qualcomm - shares his journey at Maven Silicon

The projects done during the course is very useful, once you get into the industry. The curriculum has been designed really well and sets you on a correct path to pursue your career in semiconductor industry.

Saurabh Ramesh Jaipurkar joined PerfectVIP - shares his journey at Maven Silicon

My journey from an Asst Prof to Verification Engineer could only get possible with the Industry standard VLSI training from Maven Silicon.

Giradha Meghana joined Synopsys – shares her journey at Maven Silicon

Along with Good course structure and training methods, 24/7 online support, communication sessions, doubt clarification classes are the key highlights of training at Maven Silicon

Nikhil Satish joined ARM

Awesome!!! The entire team is amazing, dedicated and the work culture is top notch.... Proud Mavenite Forever!!!!

Amith Patil joined Mediatech

If you want to get into semiconductor industry, you should join Maven Silicon. The faculty here are experienced and give students in-depth knowledge of the subjects.

Sujay R Kanikraj joined Juntran

Any IT folks interested in changing their domain to VLSI field then I feel Maven must be their top choice. Highly professional trainers and well-organized labs sessions give you very deep knowledge about the subject. With their continuous placements assistance, it’s very helpful to get into the industry.

Ram Babu joined Qualcomm

I have been trained in Maven-Silicon and I felt its worth to join here. Subjects will be taught by industrial experts and you can get hands on experience since there will be more practical sessions than theoretical. They will provide 100% placement assistance.

Rakesh Kumar joined Wafer Space

At Maven, they teach us from basics like Digitals, Verilog and verification methodologies like UVM. They concentrate on lab sessions more than theory classes to get practical knowledge including projects.

Priyanka Hiremath joined Mirafra Technologies

very easy to understand through simple explanations and the course was just the right mix of theory and practical demonstration. I have gained the knowledge that I can quickly and easily apply in my workplace.

Why Maven Silicon?

Dynamic
Course structure

Highly qualified
faculties

State-of-
art infrastructure

Hands-on
Training

24*7 Lab
Access & Support

Technical group
discussion

MASS
(24*7 online support)

1:1 mentoring

Admission Process

Recommended Background

BE/BTech in EEE/ECE/TE/CSE/IT/Instrumentation

ME/MTech/MS in Electronics/MSc Electronics

Prerequisite - Good knowledge of Verilog

Fill the application form

APPLY NOW

Batch Calendar

Nov 30^th
2019

Mar 7^th
2020

May 9^th
2020

Payments

Candidates can pay the Course fees through

Net Banking

Credit/Debit
Card

Cheque, DD

DEMO CLASS

DOWNLOAD BROCHURE

APPLICATION FORM

FAQ

What is the eligibility criteria for this VLSI course?

You should be: BE/BTech Graduate with Online VLSI Design Methodologies course Certificate (https://elearn.maven-silicon.com/vlsi-design-course) OR BE/BTech with minimum one-year experience in VLSI Design OR BE/Btech/ME/Mtech/MS with very good knowledge in RTL Design and Verilog HDL

What are the prerequisite topics required to join the ASIC Verification Course ?

Digital Electronics and RTL Design using Verilog Coding Concepts are prerequisite topics required to join this VLSI Course. You can also learn these topics through our Online Design Methodologies Program available on our elearn portal. https://elearn.maven-silicon.com/vlsi-design-course

What kind of extra support will be given during the course?

Free VLSI Video tutorials of all the modules of Advanced ASIC Verification course will be provided through our learning managing system for extra practice

Can I do the labs and projects from home?

Yes, you can do the labs and projects from home as we provide 24/7 Lab access through VPN.

When am I supposed to pay the fee?

After your selection for the admission, you are required to block your seat by paying the registration fee in advance. The remaining fee has to be paid on reporting day of the course.

Can I bring my laptop?

We are equipped with 200+ laptops/computers to support your learning process. Also, we strictly prohibit the use of your personal laptops/storage device in the premises under the copyright and trademark infringement act.

I am working for 2 years in VLSI domain but still do not understand many concepts completely. How can I become pro in ASIC verification?

You require to learn more and develop your concepts. In part time ASIC Verification Course, you can learn SystemVerilog, UVM, Assertion Based Verification - SVA, Verification Planning and Management, Code and Functional Coverage, Perl scripting language and VIP coding style through easy to understand theory concepts and continuous practice and implementation of the concepts in Labs. This extra acquired knowledge will make you a pro at work.