Job Oriented Advanced VLSI Course

Module 1

Introduction to VLSI

• VLSI Design Flow
• ASIC Vs FPGA
• RTL Design Methodologies
• Introduction to ASIC
  Verification Methodologies

VLSI Design Flow Steps - Demo

Module 2

Introduction to Linux

• Components of UNIX system
• Directory Structure
• Utilities and Commands
• Vi Editor

Module 3

Advanced Digital Design

• Introduction to Digital Electronics
• Arithmetic Circuits
• Data processing Circuits
• Universal Logic Elements
• Combinational Circuits - Design and Analysis
• Latches and Flip flops
• Shift Registers and Counters
• Sequential Circuits - Design and Analysis
• Memories and PLD
• Finite State Machine

Microcontroller Design

Module 4

Static Timing Analysis

• Introduction to STA
• Comparison with DTA
• Timing Path and Constraints
• Different types of clocks
• Clock domain and Variations
• Clock Distribution Networks
• How to fix timing failure

Module 5

CMOS Fundamentals

• Non Ideal characteristics
• BJT vs FET
• CMOS Characteristics
• CMOS circuit design
• Transistor sizing
• Layout and Stick Diagrams
• CMOS Processing Steps
• Fabrication
• CMOS Technology - Current Trends

Module 6

Verilog HDL - RTL Coding and Synthesis

[1] Introduction to Verlog HDL

• Applications of Verilog HDL
• Verilog HDL language concept
• Verilog language basics and constructs
• Abstraction levels

[2] Data Types

• Type Concept
• Nets and registers
• Non hardware equivalent variables
• Arrays

[3] Verilog Operators

• Logical operators
• Bitwise and Reduction operators
• Concatenation and conditional
• Relational and arithmetic
• Shift and Equality operators
• Operators precedence

[4] Assignments

• Type of assignments
• Continuous assignments
• Timing references
• Procedures
• Blocking and Non-Blocking assignments
• Execution branching
• Tasks and Functions

[5] Finite State Machine

• Basic FSM structure
• Moore Vs Mealy
• Common FSM coding styles
• Registered outputs

[6] Advanced Verilog for Verification

• System Tasks
• Internal variable monitoring
• Compiler directives
• File input and output

[7] Synthesis Coding Style

• Registers in Verilog
• Unwanted latches
• Operator synthesis
• RTL Coding style

Module 7

Code Coverage

• Statement coverage
• Branch Coverage
• Expression Coverage
• Path Coverage
• Toggle Coverage
• FSM - State, Arc and Sequence coverage

Module 8

FPGA Architecture

[1] PLD

• General Structure and Classification
• CPLD Vs FPGA

[2] Xilinx CPLD - Xc9500

• Block Diagram of CPLD
• Detailed study of each block
• Endurance limits
• Timing Model

[3] Xilinx FPGA

• FPGA Architecture
• CLBs and Input/Output Blocks
• Luts, SLICE DFFs
• Dedicated MUXes
• Programmable Interconnects
• Architectural Resources
• Power Distribution and Configuration

[4] FPGA Architecture of Different Xilinx Families

[5] Netlist and Timing simulation

Module 9

Verilog Mini Project RTL Coding and Synthesis

• Project Specification Analysis
• Understanding the architecture
• Module level implementation and verification
• Building the top level module
• Implementing the design into the FPGA board

Module 10

Design Automation using Scripts Perl

• Introduction to Perl
• Functions and Statements
• Numbers, Strings, and Quotes
• Comments and Loops

Module 11

Soft Skill Workshop

• Communication Skills
• Mock up interview
• Group Discussion
• Behavioural traits
• Interpersonal skills
• Time and Project Management

Module 12

ASIC Verification Methodologies

• Directed Vs Random
• Functional verification process
• Stimulus Generation
• Bus function model
• Monitors and reference models
• Coverage Driven Verification
• Verification Planning and management

Module 13

System Verilog HVL

[1] Introduction to System Verilog

• New Data types
• Tasks and Functions
• Interfaces
• Clocking blocks

[2] Object Oriented Programming and Randomization

• OOP Basics
• Classes - Objects and handles
• Polymorphism and Inheritance
• Randomization
• Constraints

[3] Threads and Virtual Interfaces

• Fork Join
• Fork Join_any
• Fork Join_none
• Event controls
• Mailboxes and semaphores
• Virtual Interfaces
• Transactors
• Building verification environment
• Testcases

[4] Callbacks

• Facade Class
• Building Reusable Transactors
• Inserting Callbacks
• Registering Callbacks

[5] Direct Programming Interface

[6] Functional Coverage

• Coverage models
• Coverpoints and bins
• Cross coverage
• Regression testing

Module 14

Verification Planning and Management

• Verification Plan
• TB Architecture
• Coverage Model
• Tracking the simulation process
• Building regression testsuite
• Testsuite optimization

Module 15

Advanced System Verilog

• Environment Configuration
• Reference Models and Predictor Logics
• Using Legacy BFMs
• Scenario Generation
• Testcases - Random,
  Directed and corner case
• Coding styles for VIP

Module 16

Assertion Based Verification - SVA

• Introduction to ABV
• Immediate Assertions
• Simple Assertions
• Sequences
• Sequence Composition
• Advanced SVA Features
• Assertion Coverage

Module 17

Verification Mini Project:
Verification and RTL sign-off

• Project specification analysis
• Defining verification plan
• Creating Testbench architecture
• Defining Transaction
• Implementing the transactors - Generator, Driver, Receiver and Scoreboard
• Implementing the coverage model
• Building the top level verification environment
• Defining weighted random, corner case and directed testcases
• Building the regression testsuite
• Generating the functional and code coverage reports

Module 18

UVM - Universal Verification Methodology

• Introduction to UVM Methodology
• Overview of Project
• UVM TB Architecture
• Stimulus Modeling
• Creating UVCs and Environment
• UVM Simulation Phases
• Testcase Classes

• TLM Overview
• Configuring TB Environment
• UVM Sequences
• UVM Sequencers
• Connecting DUT- Virtual Interface
• Virtual Sequences and Sequencers

• Creating TB Infrastructure
• Connecting multiple UVCs
• Building a Scoreboard
• Introduction to Register Modeling
• Building reusable environments

Module 19

Interfaces and Protocols

• Guest Lectures by Industry Experts

Module 20

Industry Standard Project

• Design specification analysis
• Creating the design architecture
• Partitioning the design
• RTL coding in Verilog
• RTL functional verification
• RTL Synthesis
• Place & Route the netlist
• Timing Simulation

EDA Tools

• Mentor Graphics
• Xilinx
• Aldec

Operating System

• Linux - Ubuntu