VLSI Interview Questions and Answers

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VLSI Interview Questions

Q: Find the radix in the following expression 121(r) = 144(8)

(1 x r2) + (2 x r1) + (1 x r0) = (1 x 82) + (4 x 81) + (4 x 80)

r2 + 2r + 1 = 64 + 32 + 4

r2 + 2r + 1 = 100

(r +1)2 = 102

(r +1) = 10

r = 9

Q:

Q: For the following circuit ,find the output.

Q: List out the differences between Combinational & Sequential circuits

Q: What do you mean by modulus of a counter? what is the modulus of decade counter?

The number of counts a counter can count before returning to its original value is called as modulus of a counter. Modulus of decade counter is MOD-10

Q: For JK flip-flop if J=K=0, Clock is supplied with 10MHz square wave. What will be the o/p frequency?

As the output remains the same. So the frequency of constant output voltage is Zero

Q: What is set-up time and hold time?

Setup Time (Tsu) is the minimum time interval for which the input signal must be stable (unchanging) prior to the sampling event of the clock for the input signal to be recognized correctly.

Hold Time (Th) is the minimum time interval for which the input signal must be stable (unchanging) following the sampling event of the clock for the input signal to be recognized correctly.

Q: Define Propagation delays C2Q,S2Q and R2Q of flip-flops

C2Q: For an edge-triggerred flip-flop, the clock-to-Q time is the time it takes for the flipflop output to be in a stable state after a clock edge occurs.

S2Q, R2Q: It is the time taken by flipflop to come to SET or RESET state after the application of asynchronous inputs.

Q: Convert JK Flip-Flop into D FF

System verilog Interview questions

Q: What is the difference between code coverage & functional coverage?

Code coverage measures how much of the code has been executed(statement,branch,expressions in the RTL code).

Functional coverage will be defined by the user. User will define the coverage points for the functions to be covered in DUT based on the functional specification. This is completly under user control

Q: What is virtual class in System verilog?

A virtual class is a class for which instance or object can not be constructed but you can define the handle to the virtual class. They are used to create code that can be shared across multiple projects Pure virtual methods can be defined as templates in the virtual class. Basically it forces all extended classes to implement the functions.

Q: What is difference between reg,logic & wire datatypes in System Verilog?

Reg - 4 state data type. Reg is a date storage element. Its not a actual hardware register but it can store values. Register retain there value until next assignment statement. The reg data can be driven assigned values inside the procedural block. Default value is "x" wire - 4 state data type. Wire data type is used in the continuous assignments or ports list. It is treated as a wire, so it can not hold a value. It can be driven and read. Default value is "z" logic - 4 state data type, similar to reg. The main difference between logic data type and reg/wire is that a logic can be driven by both continuous assignment or blocking/non blocking assignment. Default value is "x"

Q: Difference between module & class based TB?

A module is a static object present always during the simulation.

A Class is a dynamic object because they can come and go during the life time of simulation.

Q: Why do we use create method in uvm rather than using new constructor?

We use create() method because, if any overrides are registered with the factory, the create method returns object of override type(by type I mean type of class). So, basically we get child object on parent handle if overrides are registered. Whereas new() method returns object of type its being called on.

Q: Why we are using mailboxes to establish the connection between the TB components instead of queues?

Queue is an unpacked array which grows & shinks automatically. It can be used to model FIFO,LIFO.We can insert & delete the elements from the first, last & in between also.Mailbox is an higher level concept that is built around a combination of queues and semaphores. If you have only one process reading and writing to the data structure, there is no need to use a mailbox. However if there are more than one thread, a mailbox is a convenient class to use because of blocking methods put & get. But if you have multiple threads, and need access to any position in the queue, you will need to write your own class to do that.

Q: How UVM phases are initiated?

UVM phases are initiated by calling run_test from top module. run_test first creates test & initiates all phases sequentially

Q: Why we need to use assertions?

Assertions improves both observability and controllability so, that, we can trace the cause of the bug very quickly.

Q: What is polymorphysim?

When base class handle is pointing to child class object,we can access the child methods provided that child class should override the virtual methods of parent

Q: Why we use virtual interface in SV?

SystemVerilog interface is static in nature, whereas classes are dynamic in nature, because of this reason, it is not allowed to declare the interface within classes, but it is allowed to refer to or point to the interface. A virtual interface is a variable of an interface type that is used in classes to provide access to the interface signals. Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals that make up the design. A virtual interface allows the same subprogram to operate on different portions of a design and to dynamically control the set of signals associated with the subprogram. Instead of referring to the actual set of signals directly, users are able to manipulate a set of virtual signals. Changes to the underlying design do not require the code using virtual interfaces to be rewritten. By abstracting the connectivity and functionality of a set of blocks, virtual interfaces promote code reuse.

Verilog interview questions

Q: What do you mean by synthesizable Verilog?

A subset of the language Verilog features that are well supported by synthesis tool.

Q: For combinational circuit synthesis, which of the following are recommended?

If “if…else” construct is used, value must be assigned to the output variable for all possible combinations of the inputs.

Q: Which one is true related to FSM?

Present State Logic should be synchronous to the clock

Q: What is an event?

An event is a change in a net or variable type.

Q: Which one is true for a task?

Tasks are synthesizable without delay.

Q: What is an event? Which event is used to infer Flipflops?

An event is a change in a register or net type. Pos-edge or neg-edge triggered events are used to infer Flipflops.

Q: What is true about a Testbench?

Testbench is a behavioral model and doesn’t have port list.

Q: What is the correct syntax for declaring a real number?

real r;

Q: What is correct for an array?

An array is a stack of registers.

Q: What is used in Verilog to customize simulation time?

`timescale compiler directive