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Key Features of Online VLSI DM

Live Q&A Sessions for doubt clarification

Hard copy support material

Labs with EDA tools for hands-on experience

Project - Complete lifecycle from architecture design to synthesis

About the Instructor

The entire course is designed and delivered by CEO Mr. P R Sivakumar, a seasoned engineering professional with 20+ years of experience in Industry and Academia.

He has worked as a Verification Consultant for the top EDA companies Synopsys, Cadence and Mentor and helped various ASIC and FPGA design houses deploy and use various verification methodologies effectively, resulting in successful tape out of SoCs and Chips.

He now specializes in offering Verification IPs and consulting services, EDA flow development and corporate training on advanced ASIC verification methodologies and technologies. He is the recipient of the "Outstanding Technical Achievement" award from Cadence Design Systems and has delivered various corporate training courses at IBM, NXP, Cypress, Broadcom, Qualcomm, ST Micro, AMD, AvagoTech, Wipro, Samsung, etc.

About Course

VLSI Design Methodologies course is a front end Online VLSI course which imparts the VLSI Design Flow, Digital Design and RTL programming using Verilog HDL.

This course starts with an overview of VLSI and explains VLSI technology, SoC design, Moore’s law and the difference between ASIC and FPGA. With this overview, it walks you through all the steps of complete VLSI Design flow and explains every step in detail. Then it covers the complete digital design, combinational, sequential and FSM designs. And finally it trains you extensively on Verilog HDL programming and makes you a hands-on RTL designer.

Coupon Code

Subscribe this VLSI DM course and get the advanced ASIC Verification course
[Worth of Rs.85,000/-] with placement support for free
- T&C apply

The Advanced ASIC Verification Course [VLSI-VM] is a job oriented course which will be delivered at Maven Silicon, Bangalore. It imparts advanced verification technologies & methodologies and trains the engineers extensively on SystemVerilog & UVM. This course helps students to acquire all the skill sets required to enter in to the VLSI Industry.

Click to know more on the Advanced ASIC Verification Course with placement support

Click to know more on the Terms & Conditions

Curriculum

1. Introduction
Lecture 1 Introduction to VLSI 27:44
Lecture 2 VLSI Design Flow 35:32
2: Digital Electronics
Lecture 3 Introduction to Digital Electronics 13:25
3: Number Systems and Codes
Lecture 4 Number Systems and Codes 37:44
Quiz 1 Knowledge Check - Number Systems and Codes 25 Questions
4: Logic Circuits
Lecture 5 Logic Circuits 55:06
Quiz 2 Knowledge Check - Logic Circuits 15 Questions
5: Combinational Circuits
Lecture 6 Combinational Circuits - I 28:25
Quiz 3 Knowledge Check - Combinational Circuits - I 10 Questions
Lecture 7 Combinational Circuits - II 44:07
Quiz 4 Knowledge Check - Combinational Circuits - II
6: Sequential Circuits
Lecture 8 Sequential Circuits - I
Quiz 5 Knowledge Check - Sequential Circuits - I
Lecture 9 Sequential Circuits - II
Quiz 6 Knowledge Check - Sequential Circuits - II
7: Finite State Machines
Lecture 10 FSM
Quiz 7 Knowledge Check - FSM
8: Memories
Lecture 11 Memories
Quiz 8 Knowledge Check - Memories
9: Verilog HDL
Lecture 12 Setting Expectations - Course Agenda
Lecture 13 Introduction to Verilog HDL
10: Data Types
Lecture 14 Data Types
Quiz 10 Knowledge Check - Data Types
11: Verilog Operators
Lecture 15 Verilog Operators
Quiz 11 Knowledge Check - Verilog Operators
12: Advanced Verilog for Verification
Lecture 16 Advance Verilog for Verification
Quiz 12 Knowledge Check - Advanced Verilog for Verification
13: Assignments
Lecture 17 Assignments
Quiz 13 Knowledge Check - Assignments
14: Structured Procedures
Lecture 18 Structured Procedures
Quiz 14 Knowledge Check - Structured Procedures
15: Synthesis Coding Style
Lecture 19 Synthesis Coding Style
Quiz 15 Knowledge Check - Synthesis Coding Style
16: Finite State Machine
Lecture 20 Finite State Machine
Quiz 16 Knowledge Check - Finite State Machine
17: Summary - Verilog HDL
Lecture 21 Summary
18: Verilog Labs
Lecture 22 Instructions - Verilog Labs
Lecture 23 Verilog Lab Manual
Lecture 24 Download the Verilog Labs Folder
Lecture 25 EDA Tools - Installation Guide
Lecture 26 EDA Tools - User Guide
Lecture 27 Solution to Lab 1
Lecture 28 Solution to Lab 2
Lecture 29 Solution to Lab 3
Lecture 30 Solution to Lab 4
Lecture 31 Solution to Lab 5
Lecture 32 Solution to Lab 6
Lecture 33 Solutions - Verilog Labs
19: Final Exam - To get Certificate
Quiz 17 Final Exam

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