SystemVerilog Interfaces

Name: Maven Silicon
Brand: Maven Silicon
Rating: 4.7 (1481 reviews)

bySivakumar P R
May 4, 2020
1 minute read
6070 Views

This video explains why we prefer SystemVerilog interfaces than Verilog port level connections to build the IPs & Chips. It also explains the difference between Verilog port level connection and SystemVerilog interface connections with the help of an example step by step in detail.

To learn SystemVerilog in detail, please explore our online verification course at https://elearn.maven-silicon.com/vlsi-verification-systemverilog-uvm

Sivakumar P R
Sivakumar P R is the Founder and CEO of Maven Silicon. He is responsible for the company's vision, business, and technology. Sivakumar is a seasoned engineering professional who has worked in various fields, including electrical engineering, academia, and semiconductors for more than 25 years. Before founding Maven Silicon, he worked in the top EDA companies Synopsys, Cadence and Siemens EDA as a verification consultant.