Verilog HDL Videos

Verilog Programming Series – Dual Port Synchronous RAM

This video explains how to write a synthesizable Verilog program for Dual Port Synchronous RAM, using Verilog parameters.

In this video blogging series, we will be explaining the Verilog coding style for various building blocks like Adder, Multiplexer, Decoder, Encoder, ALU, Flip-Flops, Counter, RAM, and FSM. Understanding the coding style of all the building blocks will help you to implement any sub-system or IP in Verilog HDL as an RTL programming expert. Stay tuned!   

To learn Verilog Programming in detail, please explore our online Design Methodologies course at 

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