Executive Certification in Physical Design and Signoff

In the AI era, chip designers are empowered with AI-powered EDA tools, silicon-proven IP libraries, and open computing solutions like RISC-V to design powerful SoCs efficiently. With these advancements, even the most complex SoCs can be implemented for next-generation electronic products. However, achieving timing closure, power optimization, and area efficiency in physical design is critical for first-pass silicon success. This is the right time for chip designers and VLSI enthusiasts to explore ASIC Physical Design methodologies—covering the complete flow from RTL to GDSII, including synthesis, floorplanning, placement, clock tree synthesis, routing, timing analysis, power optimization, and sign-off techniques for successful tape-outs.

This course provides a comprehensive foundation in VLSI Physical design and verification. Learners begin with an overview of VLSI, Moore’s Law, SoC architecture, and design flows, followed by digital logic fundamentals such as number systems, combinational and sequential circuits, FSMs, and memory design. The course advances into practical hardware design and verification using Verilog HDL programming – coding styles, FSM design, and lab exercises. It then walks you through device physics and CMOS fundamentals including MOSFET operation, CMOS fabrication, and circuit layout.

The DFT module covers verification testing, ATPG, scan insertion, and fault modelling, while automation skills are developed with Tcl and Python scripting. Students also learn version control with Git, before progressing to the ASIC physical design flow, including floor planning, placement, CTS, routing, STA, layout compaction, and physical verification (DRC, LVS, IR drop, EM). Advanced topics such as signal integrity, low-power verification with UPF, and power-aware checks are included, ensuring learners gain end-to-end expertise from RTL coding to Chip tapeout with strong hands-on exposure through structured labs and industry-aligned projects.