SystemVerilog Assertions

SystemVerilog Assertions

What are SystemVerilog Assertions?

With a lot of increase in design complexity, the effort required to verify these designs is also increasing at a faster rate. To improve the verification quality we use various methods, techniques and SystemVerilog Assertions are one important feature we use to verify the design.

But do you know what are SystemVerilog Assertions?
SystemVerilog Assertions are a piece of verification code, which checks the design in adherence to the specification which will validate the specific behavior of a design and displays a message. If the specified behavior is not exhibited by the design then the assertion fails, indicating an error in the design’s behavior.
Assertions can be checked dynamically by simulation, or statically by formal verification EDA tool that proves whether the design meets its specification requirement or not. These tools require specifications about the design’s behavior.

Assertions can provide two major information about the design,

  • Is the design working correctly?
  • How good the test case is?

SystemVerilog Assertions can also provide coverage information which makes sure a certain design specification is covered in the verification. The concept/methodology of using assertions to verify a design is called Assertion based Verification – ABV.


Also read: SystemVerilog Event Scheduler

Advantages of using SystemVerilog Assertions

  1. Assertions improve the observability and controllability of the design.
  • Observability – the ability to observe the effects of a specific, internal state, data path within the design.
  • Controllability – the ability to activate, stimulate, or sensitize a specific point within the design.
  1. Assertions improve debugging of the design.
  • It helps to capture the bugs which do not propagate to the output.
  1. Assertions can find the source of the bug faster and more accurately.
  • It helps to capture the improper functionality of the design at or near the source of the problem thereby reducing the debug time.
  1. Assertions give white box visibility to the design by providing internal test points in the design.
  2. Simplifying the diagnosis and detection of bugs by localizing the occurrence of a suspected bug to an assertion monitor, which is then checked.
  3. Assertions check design specifications and report errors or warnings in case of failure.
  4. Assertions can be re-used across a design at various levels of verification.
  5. Assertions can be parameterized so they could be reused.
  6. Assertions can be turned on/off based on the requirement.
  7. Ability to interact with C and Verilog functions.

Who writes SystemVerilog Assertions?

SystemVerilog Assertions can be written in the design as well as in the verification environment.

Design EngineersWhite box verification

  • For the Signals at the Micro Architecture level (for the signals which are not visible to Verification Engineers)

Verification EngineersBlack box verification

  • For the I/O signals of IP or SoC.

What are the challenges with SystemVerilog Assertions?

  1. The quality of the test stimulus is still critical.
    • Assertions are only useful if exercised by the test stimulus.
  2. Assertions must be defined carefully.
    • Incorrect assertions can give misleading results.
    • Debugging an assertion can be difficult.
    • How do we know when enough assertions have been written?
  3. Simulation overhead.

Also read: What is the use of SystemVerilog assertion?

Types of  SystemVerilog Assertions

  1. Immediate assertions
  2. Concurrent assertions

Immediate Assertions

An assertion that checks a condition at the current simulation time is called an immediate assertion. Immediate assertions are procedural statements that can check only a combinational condition are evaluated immediately and they cannot involve any temporal operators.

Syntax: assert (condition_to_be_checked);

Example: Immediate Assertion

Immediate assertions

As immediate assertions are instantaneously checked, they may report false failures due to multiple input changes at the same time. These unexpected multiple executions need to be avoided.

An extension to the immediate assertion is deferred immediate assertion and is used to avoid the multiple outputs or errors created due to the unexpected glitching activity on inputs in the immediate assertions.

Concurrent assertions

Concurrent assertions periodically sample the test signals and are based on clock edges. Concurrent assertion is the most valuable assertion style that can be used in design and verification environments. The concurrent assertions are executed in a three-step process, i.e  sampling the values, evaluating the test condition and executing the report in the below regions,

  • Preponed region – In this region, the values for the assertion variables are sampled. In this region, a net or variable cannot change its state. This allows the sampling of the most stable value at the beginning of the time slot.
  • Observed region- All the property expressions are evaluated in this region.
  • Reactive region- The pass/fail code (Action blocks) from the evaluation of the properties are scheduled in this region.

 Example: concurrent assertion

Concurrent assertion

 Case Study: AHB

Let us see some example assertions on AHB protocol.

  • Assertion to check write data and address during busy transfer.

Assertion to check write data and address during busy transfer

  • Assertion to check address for burst transfer wrap4 with halfword.

Assertion to check address for burst transfer wrap4 with halfword

  • Assertion to check the boundary alignment for Word

Assertion to check the boundary alignment for Word

  • Assertion to check address for incremental burst.

Assertion to check address for incremental burst

Also read: How do I learn SystemVerilog in a week?


In assertion-based verification, the assertions are used to capture design intent in a verifiable form providing a mechanism to check for correct behavior. During simulation, assertions improve controllability and observability, making the source of an error evident and the simulation debug time is also greatly reduced.

Assertion-based verification is a multi-faceted approach to verifying a collection of partial specifications more efficiently. SystemVerilog Assertions enable capabilities for both simulation and formal verification and directly address the limitations of today’s verification flows.

Hope you have enjoyed this introduction and you can look forward to the next article which will discuss the use of implication in assertions and its importance in assertions.

To learn SystemVerilog in detail, explore our Advanced ASIC Verification Course.

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Technical Lead
Sinduja is focused on effective front-end verification training for our learners and her articles provide solid fundamental knowledge for the readers.