Online VLSI Verification| SystemVerilog & UVM Tutorial |SoC Verification|Verilog

1. Verification Methodology Overview
Lecture 1	Introduction to Verification Methodology
Lecture 2	Verification Process
Lecture 3	Reusable TB
Lecture 4	Verification Environment Architecture
Lecture 5	Constraint Random Coverage Driven Verification
Lecture 6	Verification Methodologies & Summary
Quiz 1	Knowledge Check
2: SystemVerilog Language Concepts
Lecture 7	SV Concepts Agenda
Lecture 8	SV Overview
Lecture 9	SV Transactions
Lecture 10	SV Interface
Lecture 11	SV Virtual Interface
Lecture 12	SV OOP
Lecture 13	SV Randomization & Functional Coverage
Lecture 14	SV TB Architecture
Quiz 2	Knowledge Check - SV Concepts
3: SystemVerilog Datatypes
Lecture 15	SystemVerilog Introduction & Logic Data Type
Lecture 16	SV Data Types - 2 State, Struct & Enum
Lecture 17	SV Data Types - Strings,Packages & Summary
Quiz 3	Knowledge Check - Data Types
4: SystemVerilog Memories
Lecture 18	SV Memories - Introduction, Packed and Multi Dimensional Arrays
Lecture 19	SV Memories - Dynamic Arrays & Queues
Lecture 20	SV Memories - Associative Arrays, Array Methods & Summary
Quiz 4	Knowledge Check - Memories

1. Verification Methodology Overview

Lecture 1

Introduction to Verification Methodology

Lecture 2

Verification Process

Lecture 3

Reusable TB

Lecture 4

Verification Environment Architecture

Lecture 5

Constraint Random Coverage Driven Verification

Lecture 6

Verification Methodologies & Summary

Quiz 1

Knowledge Check

2: SystemVerilog Language Concepts

Lecture 7

SV Concepts Agenda

Lecture 8

SV Overview

Lecture 9

SV Transactions

Lecture 10

SV Interface

Lecture 11

SV Virtual Interface

Lecture 12

SV OOP

Lecture 13

SV Randomization & Functional Coverage

Lecture 14

SV TB Architecture

Quiz 2

Knowledge Check - SV Concepts

3: SystemVerilog Datatypes

Lecture 15

SystemVerilog Introduction & Logic Data Type

Lecture 16

SV Data Types - 2 State, Struct & Enum

Lecture 17

SV Data Types - Strings,Packages & Summary

Quiz 3

Knowledge Check - Data Types

4: SystemVerilog Memories

Lecture 18

SV Memories - Introduction, Packed and Multi Dimensional Arrays

Lecture 19

SV Memories - Dynamic Arrays & Queues

Lecture 20

SV Memories - Associative Arrays, Array Methods & Summary

Quiz 4

Knowledge Check - Memories

5: SystemVerilog Tasks & Functions
Lecture 21	SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
Lecture 22	SV Tasks & Functions - Pass by value & ref and Summary
Quiz 5	Knowledge Check - Tasks & Functions
6: SystemVerilog Interfaces
Lecture 23	SV Interfaces - Introduction & Verilog ports Vs SV Interface
Lecture 24	SV Interfaces - Modports & Clocking Block
Lecture 25	SV Interfaces - Examples & Summary
Quiz 6	Knowledge Check - Interfaces
7: SystemVerilog Object Oriented Programming - Basics
Lecture 26	SV OOP - Introduction, Class Data Type & Objects
Lecture 27	SV OOP - Constructor, Null Object, Object assignments and copy
Lecture 28	SV OOP - Shallow Vs Deep Copy & Summary
Quiz 7	Knowledge Check - OOP Basics
8: SystemVerilog Object Oriented Programming - Advanced
Lecture 29	SV OOP - Introduction, Inheritance & Super
Lecture 30	SV OOP - Static properties & methods and Pass by ref
Lecture 31	SV OOP - Polymorphism, $cast, Virtual & Parametrised classes, Summary
Quiz 8	Knowledge Check - OOP Advanced
9: SystemVerilog Randomization
Lecture 32	SV Randomization - Introduction, rand and randc
Lecture 33	SV Randomization - Randomize(), Pre and Post randomize & Constraints
Lecture 34	SV Randomization - Set Membership, Constraints & Summary
Quiz 9	Knowledge Check - Randomization
10: SystemVerilog Threads
Lecture 35	SV Threads , Events, Mailbox and Semaphores
Quiz 10	Knowledge Check - Threads & Mailboxes
11: SystemVerilog Virtual Interface
Lecture 36	SV Virtual Interface - Introduction, Implementation & Examples
Quiz 11	Knowledge Check - VIF
12: SystemVerilog Functional Coverage
Lecture 37	SV Functional Coverage - Introduction & CRCDV
Lecture 38	SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Quiz 12	Knowledge Check - Functional Coverage
13: SystemVerilog Case Studies
Lecture 39	SystemVerilog Case Studies - Will be discussed during Live Q & A Session
14: SystemVerilog Reference Book
Lecture 40	SystemVerilog Reference Book
15: Universal Verification Methodology Overview
Lecture 41	Introduction to UVM
Lecture 42	UVM Concepts
Lecture 43	UVM SoC TB
Lecture 44	UVM AHB UVC
Lecture 45	UVM SoC TB Examples

5: SystemVerilog Tasks & Functions

Lecture 21

SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task

Lecture 22

SV Tasks & Functions - Pass by value & ref and Summary

Quiz 5

Knowledge Check - Tasks & Functions

6: SystemVerilog Interfaces

Lecture 23

SV Interfaces - Introduction & Verilog ports Vs SV Interface

Lecture 24

SV Interfaces - Modports & Clocking Block

Lecture 25

SV Interfaces - Examples & Summary

Quiz 6

Knowledge Check - Interfaces

7: SystemVerilog Object Oriented Programming - Basics

Lecture 26

SV OOP - Introduction, Class Data Type & Objects

Lecture 27

SV OOP - Constructor, Null Object, Object assignments and copy

Lecture 28

SV OOP - Shallow Vs Deep Copy & Summary

Quiz 7

Knowledge Check - OOP Basics

8: SystemVerilog Object Oriented Programming - Advanced

Lecture 29

SV OOP - Introduction, Inheritance & Super

Lecture 30

SV OOP - Static properties & methods and Pass by ref

Lecture 31

SV OOP - Polymorphism, $cast, Virtual & Parametrised classes, Summary

Quiz 8

Knowledge Check - OOP Advanced

9: SystemVerilog Randomization

Lecture 32

SV Randomization - Introduction, rand and randc

Lecture 33

SV Randomization - Randomize(), Pre and Post randomize & Constraints

Lecture 34

SV Randomization - Set Membership, Constraints & Summary

Quiz 9

Knowledge Check - Randomization

10: SystemVerilog Threads

Lecture 35

SV Threads , Events, Mailbox and Semaphores

Quiz 10

Knowledge Check - Threads & Mailboxes

11: SystemVerilog Virtual Interface

Lecture 36

SV Virtual Interface - Introduction, Implementation & Examples

Quiz 11

Knowledge Check - VIF

12: SystemVerilog Functional Coverage

Lecture 37

SV Functional Coverage - Introduction & CRCDV

Lecture 38

SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary

Quiz 12

Knowledge Check - Functional Coverage

13: SystemVerilog Case Studies

Lecture 39

SystemVerilog Case Studies - Will be discussed during Live Q & A Session

14: SystemVerilog Reference Book

Lecture 40

SystemVerilog Reference Book

15: Universal Verification Methodology Overview

Lecture 41

Introduction to UVM

Lecture 42

UVM Concepts

Lecture 43

UVM SoC TB

Lecture 44

UVM AHB UVC

Lecture 45

UVM SoC TB Examples

Admission

Do you have a demo session for the courses?

Yes, you can watch free demo video or watch free preview session of the course by registering on our E-learning portal https://elearn.maven-silicon.com/vlsi-verification-systemverilog-uvm

What is the prerequisite to join this course?

The eligibility criteria for the online VLSI verification course is an engineering graduate or postgraduate in the stream of electronics or electricals with good knowledge in RTL design using Verilog HDL.

How can I take the admission for Maven Silicon VLSI online courses?

You can browse for a variety of online VLSI courses and subscribe directly from our portal https://elearn.maven-silicon.com/vlsi-verification-systemverilog-uvm. We also have free VLSI courses on various topics i.e. Verilog, SoC. You can enquire with us to know about the same.

Are there any offers/ Discount available for online VLSI Courses?

You can browse for a variety of online VLSI courses and the discounts available for the same at our portal https://elearn.maven-silicon.com.

Do you have any entrance exam?

There is no entrance exam for online VLSI Verification course .

Why should I take up an online verification course instead of offline?

You can opt for online or offline course but you must choose the right mode considering the time you can spend and the flexibility you need. The online VLSI verification course also provides you Live Q&A, doubt clarification, handy technical support and reference material. So, it is a great offering with best of both worlds. You can learn on the go along with your regular office hours and upskill yourself. With Maven Silicon's Online VLSI Verification course, you can master verification concepts even if you stay in a remote corner of the world.

Course Fee

Do I have to pay the entire fee in one go?

Yes, in order to activate the course you need to make the complete payment. The Online VLSI Verification course is available on a minimal price and we also have free addon online VLSI courses on our portal https://elearn.maven-silicon.com/

Will I receive any proof after paying the fees?

The Invoice with our GSTN number will be emailed to the registered email id within 2 days.

Course Information

Where can I find the course syllabus?

Click here to explore the complete syllabus and other details for Online VLSI Verification Course https://elearn.maven-silicon.com/vlsi-verification-systemverilog-uvm

Do you provide a certificate after completion of the course?

Yes. All our courses are certification courses. The certificate will get issued after the successful completion of the course.

May I know about the trainer?

The Online VLSI Verification course is designed and delivered by our CEO Mr. SivaKumar P R who holds 20+ years of experience in industry & academia.

Can I complete the Online VLSI Verification Course in 1 month?

Yes. You can complete the course before the designated time if you spend more time on a daily basis. After completion of the Online VLSI Verification Course, you can avail up to 100% scholarship based on your grades for our Advanced ASIC Verification Classroom training with placement support.

What options do I have after completing the online VLSI Verification course?

After completing the online VLSI Verification course, you can easily crack college campus interviews or you can upgrade your job oriented skills with our job oriented Advanced ASIC Verification course with 100% placement assistance.

What are the perks of doing the online VLSI Verification course?

You can learn at your own pace & also you can revise when needed.

Is there an option to pause the course for some days?

Yes, the Online VLSI Verification course can be paused for some days and resumed later.

I am a student / working professional, will the timings be comfortable for me?

Yes, This online VLSI course has been specially designed to suit your busy schedule. You can finish this course in 3 months by spending just one hour every day. The course can be accessed anytime from anywhere as per your convenience through Laptop or Mobile App.

Which verification courses are available online?

The online verification courses available are

VLSI Verification which consists of Verification overview, SystemVerilog Theory concepts, and Universal Verification Methodology Overview
SystemVerilog for Verification
SystemVerilog HVL hands-on
Universal Verification Methodology UVM 5. Assertion based Verification SVA

Where can I access the online verification courses?

To access the online verification courses, you can click on this link https://elearn.maven-silicon.com/vlsi-verification

How can I access labs for SystemVerilog?

You can access the SystemVerilog labs by registering for SystemVerilog HVL_ Hands-on course. To register please click on this link https://elearn.maven-silicon.com/systemverilog-hvl-labs

Where can I access labs for the VLSI Verification course?

VLSI Verification consists of Verification overview and SystemVerilog Theory concepts. For labs, you can register for the SystemVerilog HVL_ Hands-on course. Click on https://elearn.maven-silicon.com/systemverilog-hvl-labs to register.

How can I do the labs for UVM (Universal Verification Methodology)

You can learn the detailed concepts of UVM and practice the labs through this course https://elearn.maven-silicon.com/universal-verification-methodology-vlsi-verification. UVM course comprises both theory and lab sessions under the same course. You can access the labs by connecting to the Maven Silicon server through a VPN. The guide for VPN configuration will be available as you register for the course.

Can I practice Verification labs from home on my laptop?

Yes, you can work on labs from your home by connecting to the Maven Silicon server through a VPN. The guide for VPN configuration will be available as you register for the course.

For how long can I access the Verification course?

Every course has a different validity, which is mentioned as you click on the course at our elearn portal. To explore, click on https://elearn.maven-silicon.com/vlsi-verification

Do I also have access to Q&A sessions for Verification courses?

Yes! When you register for the VLSI Verification course you will have access to our live Q&A sessions as a part of the course.

I have just started my career as a Verification Engineer. Will Online Verification Course help me upskill?

Definitely. The Online Verification Course will help you become a Verification expert by learning the implementation of testbench structure/VIP components and verification of a new design/IP.

Placement

How will the online VLSI Verification course certification help me to get a job in VLSI Industry?

Online VLSI Verification course helps you to get a strong foundation in Verification Methodology, SystemVerilog and Universal Verification Methodology. It helps you set foot in core companies. The certificate from Maven Silicon adds a lot to your resume and Linkedin profile.You can also take up our Advanced ASIC Verification course with 100% placement assistance by completing the Online VLSI Verification course and can avail up to 100% scholarship based on your grades.

How can I get into VLSI Industry being a fresher?

Online VLSI Verification course will help you to start learning the fundamentals required for VLSI Industry during your graduation. And then you can upgrade your skills with our job oriented Advanced ASIC Verification course with 100% placement assistance. VLSI Industry needs skilled candidates with good command on Verilog HDL, SystemVerilog HVL, UVM. You will learn all the advanced concepts in our job oriented VLSI Courses.

Support

What kind of support will I get during the course?

The online VLSI Verification course comes with labs, knowledge checks, access to course videos, and technical expert’s guidance for clarifying doubts to ensure a great learning experience.

What if I miss any session of course, can I watch it again?

Each session of course module is recorded and you will have the option to view the recorded videos multiple times at your convenience.

What if I couldn’t complete the course on time? Can I get an extension or can it be renewed again?

Yes, you can renew the course with an extension of validity at a minimal cost.

Will you provide any course materials?

Yes. Every course comes with a downloadable pdf which can be used as a reference material.

What do I do if I have any technical queries?

We have multiple channels to support you for your technical queries.

You can email us
Text us on the WhatsApp group that you will be a part of post registering for the course.
Also, you can engage with us on the discussion forum at elearn portal
Your queries would be answered in 1-2 working days through either of these channels.

Online VLSI Verification Course

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YadhuKrishnan

Sneka K