RTL coding – Synthesis

Featured Video Play Icon

This video explains the concept of logic synthesis, how we produce the digital circuit as a Gate Level Netlist through the EDA tool logic synthesizer, and why the RTL coding style is important for creating the synthesizable models. Also it explains how we create the EDA independent synthesizable models with a few examples like registers and resource sharing/optimization.

To learn Verilog Programming in detail, please explore our online Design Methodologies course at  https://elearn.maven-silicon.com/vlsi-design-course 

Related Posts