Maven Silicon – a RISC-V Training Partner
We are delighted to collaborate with RISC-V and empower the engineering community to innovate and create new and powerful chips, primarily using open.
Author: Sivakumar P R
Importance of Internship for Engineering Students
Every university/college is making the internship mandatory and asking their UG students to do it while doing the engineering course itself. However, it used to be only for the PGs. I feel it’s a g...
Newsletter August 2020
The world in the last quarter has seen a massive change with a significant impact on businesses. Needles to say, the Learning and Development Industry has taken this challenge head-on! Here is our st...
Maven Silicon featured in Business India Magazine
Business India magazine interviewed our Founder and CEO Mr. P R Sivakumar, VP Mr. Catakam Kumar, and our alumnus, and published this article meritoriously.
It beautifully narrates our founder’s jo...
SystemVerilog – Class based Verification environment
This video explains why we prefer Object Oriented Programming to create the class-based verification environment in SystemVerilog...
Verification IP Vs Testbench
Anyone can create a testbench and verify the design, but it can’t be simply reused as a verification IP. Most of the module/IP level testbenches are used once to verify the design. We always want t...
Where are we heading in the Semiconductor business?
I am glad to address this question and explain to those who might always be wondering and asking everyone in the industry ‘Where are?’
Code Coverage
Though we use both code and functional coverage to sign-off the design verification, they are not the same. So, you need to understand what is code coverage and how it is used to improve the quality.
Is it worth learning SystemVerilog in college itself?
It’s definitely worth it, but not mandatory to get into the semiconductor industry. SystemVerilog is the most preferred language for the IP & Sub-system verification that demands constrained.
How do I get a job in ASIC/FPGA verification?
As a verification engineer, you should be good at finding bugs in the design and disproving the designer, while verifying and proving the design [DUT/DUV] functionality as per.
