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July 27, 2022 Sivakumar P R 0
RISC VS CISC
RISC is a Reduced Instruction Set Computer. We prefer RISC primarily for...
Blog RISC-V Verification Videos VLSI Industry VLSI Training 
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June 17, 2020 Sivakumar P R 0
SystemVerilog – Class based Verification environment
This video explains why we prefer Object Oriented Programming to create the...
Verification Videos 
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June 4, 2020 Sivakumar P R 0
SystemVerilog OOP – Polymorphism
This video explains how we use Object Oriented Programming feature Polymorphism to...
Verification Videos 
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May 18, 2020 Sweety Dharamdasani 0
Create a winning LinkedIn profile
Did you know? A hire is made every 10 seconds using LinkedIn....
Videos VLSI Training 
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May 15, 2020 Sivakumar P R 0
UVM SoC Testbench
This video explains how we reuse the IP level UVM test benches...
Verification Videos 
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Newsletter August 2022

Newsletter August 2022

September 2, 2022 0
Physical Design Flow

Physical Design Flow

August 29, 2022 1
Clock Domain Crossing

Clock Domain Crossing

August 26, 2022 0
SoC Verification Flow and Methodologies

SoC Verification Flow and Methodologies

August 20, 2022 1

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    RISC VS CISC

    July 27, 2022 Sivakumar P R 0
    RISC is a Reduced Instruction Set Computer. We prefer RISC primarily for battery-operated light-weight applications like IoT devices that use embedded system controllers or mobile phones that use SoCs.
    Blog RISC-V Verification Videos VLSI Industry VLSI Training 

  • SystemVerilog – Class based Verification environment

    June 17, 2020 Sivakumar P R 0
    This video explains why we prefer...
    Verification Videos 

  • SystemVerilog OOP – Polymorphism

    June 4, 2020 Sivakumar P R 0
    This video explains how we use...
    Verification Videos 

  • Create a winning LinkedIn profile

    May 18, 2020 Sweety Dharamdasani 0
    Did you know? A hire is...
    Videos VLSI Training 

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    Newsletter August 2022

    September 2, 2022 Sivakumar P R 0
    Creating a state-of-art destination for the...
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  • Physical Design Flow

    Physical Design Flow

    August 29, 2022 Putta Satish 1
    In this article, let me explain...
    Blog Physical Design Verification VLSI Industry VLSI Training 
  • Clock Domain Crossing

    Clock Domain Crossing

    August 26, 2022 Shanthi V A 0
    Today’s device needs multiple clocks with...
    ASIC Verification Blog Digital Electronics Verification VLSI Industry VLSI Training 

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Maven Silicon
  • Home
  • About Us
    • About Us
    • CEO’s message
    • Partners
    • Why Maven Silicon?
  • Blog
  • Admissions
    • Application
    • Training Calendar
    • Online Test
  • Program Offerings
    • Job Oriented Course
      • Advanced VLSI Design and Verification Course – [VLSI RN]
      • Blended Learning VLSI Program – [Blended VLSI RN]
      • Advanced ASIC Verification Course – [VLSI VM]
    • Corporate Training
    • Online VLSI Courses
    • Online VLSI Design Methodologies [ VLSI DM ]
    • VLSI Internship
    • Part time VLSI Courses
      • VLSI Design Course [VLSI DM-PT]
      • Advanced ASIC Verification Course [ VLSI VM-PT ]
  • For Organisations
    • Corporate – Hire Talent
    • Corporate Training
    • University
  • News & Events
    • Placement
    • Connect with us
    • Demo Class
    • Free VLSI Workshop
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    • Careers
      • Jobs at Maven
      • Jobs at Aceic
  • Contact Us