All Posts

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  Verilog HDL

  Reset Domain Crossing (RDC) in Digital Design

  • by  Megha P Patil
  • December 20, 2025
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  Verilog HDL

  AI Meets RTL: Intelligent Cell Selection in VLSI Design

  • by  Megha P Patil
  • December 18, 2025
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  Verilog HDL

  Designing for Power, Performance, Area (PPA) Trade-offs at RTL Level

  • by  Raghavendra H
  • December 8, 2025
• 

  Verilog HDL

  A Practical Look at specparam in Verilog

  • by  Basavaraj H
  • December 4, 2025
• 

  SoC Design

  Privilege Levels in ARM Architecture

  • by  Shanthi V A
  • December 1, 2025
• 

  Verification

  Why Formal Verification is Essential in Modern Hardware Design

  • by  Naresh Kumar Koppala
  • November 26, 2025
• 

  Verification

  Breaking Down PCIe: The Silent Force Behind Cutting-Edge Tech

  • by  Chalam Tirunagari
  • November 24, 2025
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  VLSI Industry

  Power-Aware Design and Verification: Building Low-Power, High-Performance Chips

  • by  Raghavendra H
  • November 24, 2025
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  Digital Electronics

  Frequency Division with different Duty Cycles

  • by  Shwetha A Gangannawar
  • November 22, 2025
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  Verification

  Universal Chiplet Interconnect Express (UCIe): Redefining Chiplet Communication

  • by  Chalam Tirunagari
  • November 21, 2025
• 

  Physical Design

  Challenges in Physical Design at Advanced Nodes (3nm & 2nm)

  • by  Ishita
  • November 20, 2025
• 

  DFT

  SCAN COMPRESSION IN DESIGN FOR TESTABILITY

  • by  Geetha G
  • November 19, 2025
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  VLSI Industry

  The Weekend Degree That’s Changing Careers: Executive MTech in VLSI for Working Professionals in Bangalore

  • by  Maven Silicon
  • September 27, 2025
• 

  VLSI Industry

  From Blocks to Systems: Understanding Chiplets in SoC Design

  • by  Akshaya M Ganorkar
  • September 27, 2025
• 

  Advanced Careers

  Missed Getting Into IIT? Get Trained by IIT Experts with These Top IIT Certification Courses by Maven Silicon & iHUB, IIT Roorkee

  • by  Maven Silicon
  • September 18, 2025