You can learn and get some exposure, but becoming an expert user of SystemVerilog[SV] depends on your prior programming experience in Verilog and any OOP based languages like C++/Java. Also, you need to understand the difference between SV usage for RTL coding and TB implementation. Depending on your need, design or verification, you can choose the subset of SV and focus only on it. It will save you time.
For example, if you are planning to use SV programming expertise to get a job in the semiconductor industry as a fresher, I would suggest you learn the SV for verification. To learn SV, you should be an expert user of HDL, Verilog or VHDL. If you are a VHDL guy, you can still understand the Verilog syntax and practice SV, but knowledge of Verilog HDL is a must, as SV is the superset of Verilog. Also, knowledge of OOP based languages is optional to learn the SV. With the Verilog programming expertise, you can easily learn the SV language concepts, including the Object-Oriented Programming. It depends on the author/trainer, how he/she explains the concepts. You may want to choose the right training courses/textbooks. If you have very limited time, you may want to opt for the right training courses, offline/online courses.
So, no one can say precisely whether you can learn SV in a week. It depends on your prior experience and coding expertise. To learn Verilog and SystemVerilog for verification quickly, you can refer my online course at VLSI Verification
If you are looking for a hands-on experience on complete ASIC Verification Flow, you may want to explore our offline verification courses at ASIC Verification Course | SystemVerilog Training | UVM Training Courses | Verification Methodologies