What is the use of SystemVerilog assertion?

SystemVerilog Assertion

The scoreboard in your SystemVerilog testbench or verification environment does only data integrity checking. It means that it always compares only the output packet with the expected packet or input packet. To verify the design functionality completely, we also need to verify the DUT interface protocol like AHB, AXI, USB, etc. And this kind of protocol validation as a temporal verification [in terms of clock cycles] can be achieved easily through writing assertions using the interface signals.

Designers can also embed the assertions in the RTL code for every logic to debug the simulation failures later on while running the simulation. It’s called dynamic Assertion Based Verification [ABV]. Also as per static ABV, one can use formal verification methodology and EDA tool to verify the RTL design functionality only with assertions, without writing any testbench and running simulation.

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