Executive Certification in VLSI Design for Testing

In the AI era, chip designers are empowered with AI-powered EDA tools, silicon-proven IP libraries, and open computing platforms like RISC-V, enabling the efficient design of powerful SoCs for next-generation products. However, ensuring testability and fault coverage is equally critical for first-pass silicon success. This is the right time for chip designers and VLSI enthusiasts to explore ASIC Design for Testing (DFT) methodologies—covering scan insertion, ATPG, fault modeling, BIST, boundary scan, JTAG, and advanced techniques for low-power and high-performance designs. A strong foundation in DFT ensures high-quality, reliable SoCs ready for mass production.

This course provides a comprehensive foundation in Design For Testing. Learners begin with an overview of VLSI, Moore’s Law, SoC architecture, and design flows, followed by digital logic fundamentals such as number systems, combinational and sequential circuits, FSMs, and memory design. The course advances into practical hardware design and verification using Verilog HDL programming - coding styles, FSM design, and lab exercises. It then walks you through CMOS fundamentals, Synthesis, Clock Domain Crossing, STA, Equivalence Checking, and Physical Design Flow - floor planning, placement, CTS, routing, layout compaction, and physical verification (DRC, LVS, IR drop, EM), with labs and case studies.

The Design For Testing module covers verification vs testing, scan insertion, ATPG, fault modelling, BIST, boundary Scan, Test compression, DRC & Test coverage, JTAG, DFT for Analog Macros, while automation skills are developed with Tcl and Python scripting. Students also learn version control with Git, before progressing to advanced DFT concepts and doing an industry standard project – DFT implementation on an SoC.