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VLSI Projects

Why VLSI Projects?

A very common answer from the engineering graduates on what is the most challenging part of getting a VLSI job is,  the lack of practical skills. Skill is all about hands-on experience. VLSI Projects can help you to gain the relevant experience to get into the VLSI Industry.

Skill is the quintessential requirement for every job that you opt for.  It is a capability to perform at your job. Unfortunately, One of the biggest challenges faced by the VLSI industry today is that entry-level VLSI engineers are not readily employable and they are definitely required to be skilled. VLSI Projects play a vital role in making these fresh engineering graduates employable.

Maven Silicon was invented with a vision of producing highly skilled VLSI engineers and contributing to the Semiconductor industry. Learning the Advanced VLSI Concepts, practicing the learned concepts by doing the VLSI Lab work, and the live VLSI project work at Maven Silicon is focused on enabling the young engineers before they hit the floor.

VLSI Projects are vehicles to help learners learn, change, adapt, improve, and adopt new processes, products, or technology. VLSI Projects are a part of every cours. Be it a job-oriented VLSI course, online VLSI design methodologies, or Internships. Undergraduates or Mtech graduating students can enroll in our Internship programs to design a project for their academic evaluations too. 

Here is a sneak peek of the VLSI projects we offer at Maven Silicon:

AHB to APB Bridge Verification

The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses.

Trainees should develop the TB to verify following features

  1. Sequential Write transfer(with different values of HBURST)
  2. Sequential Read transfers(with different values of HBURST)
  3. Non sequential write transfers
  4. Non sequential read transfers
  5. Non sequential back to back read & write transfers
  6. Combination of sequential & non sequential transfers

AXI4 Protocol Verification

The AMBA AXI protocol is targeted at high-performance, high-frequency system and includes a number of features that make it suitable for a high-speed submicron interconnects.

Trainees should develop the TB to verify following features

  1. Write burst transfers(increment & wrapping) with different lengths
  2. Read burst transfers(increment & wrapping) with different lengths
  3. Multiple outstanding feature
  4. Narrow transfers with aligned & unaligned address
  5. Out of order transaction
  6. All possible response

RISC-V RV32I Processor verification

The RV32I Processor is designed to support all RV32I Base Integer Instructions (Total -39). It’s a three stage pipelined processor which executes 32 bit instructions in program order.

Trainees should develop the TB to verify all the integer set instructions

Bluetooth - BLE

Bluetooth is a wireless technology standard used for exchanging data between different devices over short distances using Ultra high frequency radio waves in the industrial, scientific and medical radio bands, from 2.402 GHz to 2.480 GHz, and building personal area networks

Trainees should develop testcases to verify different types of advertising and data PDU

Router RTL design project

The Router 1x3 design follows packet based protocol and it receives the network packet from a source LAN on a byte by byte basis. The packet received is stored internally and is read by the destination LAN on a byte by byte basis. During the read operation, the packet is read in a first in first out order.

Project specification analysis

  1. Understanding the block level design architecture
  2. Developing module level RTL codes using Verilog.
  3. Verifying sub-block using Verilog TB.
  4. Building the top module
  5. Top level verification using Verilog Test bench
  6. Generating code-coverage report on the RTL

SPI RTL design project

SPI (Serial Peripheral Interface) Master core is a serial communication protocol. Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs. It has some of the features like full duplex synchronous serial data transfer with a variable length of transfer word up to 128 bits. It is WISHBONE bus compliant and act like a WISHBONE slave.

Project specification analysis

  1. Developing the block level design architecture
  2. Developing module level RTL codes using Verilog.
  3. Verifying sub-block using Verilog TB.
  4. Building the top module
  5. Top level verification using Verilog Test bench

AHB-APB RTL bridge design project

AHB-APB Bridge is an interface between multiple AHB masters and a selected APB peripheral. The bridge supports burst transfer which converts AHB transactions to APB signals. Pipelining is used on AHB slave interface to synchronize AHB address & data into phase

Project specification analysis

  1. Developing the block level design architecture
  2. Developing module level RTL codes using Verilog.
  3. Verifying sub-block using Verilog TB.
  4. Building the top module
  5. Top level verification using Verilog Test bench

PCS RTL design project

The Physical coding layer (PCS) is a GMII interface that encodes (decodes) the GMII data octets to (from) ten-bit code-groups (8B/10B) for Ethernet communication.The PCS supports auto-negotiation process.

Project specification analysis

  1. Developing the block level design architecture
  2. Developing module level RTL codes using Verilog.
  3. Verifying sub-block using Verilog TB.
  4. Building the top module
  5. Top level verification using Verilog Test bench

RISC-V 32I processor RTL design project

The RISC-V 32I processor supports base integer instructions (39). It’s a 3 stage pipelined processor which executes 32bit instructions.

Project specification analysis

  1. Analysing the block & micro level design architecture
  2. Developing module level RTL codes using Verilog.
  3. Building the top module
  4. Top level verification using UVM Test bench

RISC-V 32I processor design DFT implementation project

The RISC-V 32I processor supports base integer instructions (39). It’s a 3 stage pipelined processor which executes 32bit instructions. In this project, you will insert Boundary scan, Scan chain, EDT IP core on this 32bit processor design and implement the ATPG pattern generation using stuck-at-fault model. The design needs to be synthesized, and the gate level netlist will be used for the DFT design flow.

Project specification analysis

  1. Insert Boundary scan IJTAG components into the gate-level netlist.
  2. Insert Scan chain into the gate-level netlist.
  3. Insert EDT IP Core to the scan chain netlist.
  4. ATPG flow to obtain test patterns using Stuck-at-fault model.
  5. Report the Fault coverage & test coverage.
  6. Improve the test coverage.

Router Verification

The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Trainees should develop the TB to verify following features

  1. The packet should reach all the three destinations properly as per the channel address.
  2. All the three destinations should receive packet of all the possible payload lengths
  3. When the data is corrupted, error signal should go high
  4. When data out is not read within 30 cycles of valid out going high, soft reset should occur

UART IP core Verification

The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices.

Trainees should develop the TB to verify following features

  1. Loop back mode
  2. Half duplex mode
  3. Full duplex mode
  4. Verifying different interrupts
  5. Verifying functionality of UART in different configurations of Line control Register

SPI IP core verification

The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.

Trainees should develop the TB to verify following features

  1. Different Character Lengths
  2. Transfer with LSB as first bit
  3. Transfer with MSB as first bit
  4. MOSI on posedge & MISO on negedge
  5. MISO on posedge & MOSI on negedge
  6. Different sclk frequencies
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We offer various customized VLSI design and verification courses to the corporate engineers who want to learn the design and verification methodologies and programming languages quickly to work directly on the customer projects. Our portfolio of the courses includes RTL Design using HDL, Verilog...

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Our part time ASIC verification course has been designed for the working professionals and post graduates who want to upgrade their skills. This part time ASIC Verification course trains the engineers extensively on the Verification methodologies and help them to switch to their dream profile of ASIC Verification...

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VLSI Internship

  • Industry standard Projects
  • Internship Certificate
  • Add-on in resume

VLSI Internship program is basically for the electronics engineers who are looking for an experience on the real time VLSI projects, while pursuing the engineering course. As part of this internship program the engineering graduates will learn the VLSI Design flow and methodologies, VLSI Verification Flow and Verification methodologies...

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Our CEO Mr. Sivakumar P R is the author of our blog. He is an industry veteran who has 20+ years of experience in various fields, Academia, Engineering and Semiconductor Industries. In semiconductor industry he has worked in the top EDA companies like Synopsys, Cadence and...

Advanced VLSI Design and Verification Course

This Advanced VLSI Design and Verification course is a blended learning program, called as blended VLSI-RN course which includes both online theory sessions along with labs & projects and offline projects & internship programs.

It is designed carefully based on the industry requirements and it trains the electronics engineers extensively on both the design and verification methodologies like RTL design and UVM methodologies and make them specialized in the advanced VLSI technology domains like Design For Test, Low Power Verification, Analog Mixed Signal Verification, etc. Also our engineers work on multiple industry standard projects which use the SoC protocols and gain real time project experience through our internship program. This helps our engineers to face any tough technical interviews.

Duration: 6 months Training + 6 months Internship

Course Library

Features

  • ASIC & FPGA design methodologies
  • Training and Internship
  • Advanced Logic Design
  • FPGA Architecture
  • RISC-V Instruction Set Architecture
  • RISC-V RV32I RTL Architecture Design
  • ASIC Verification Methodologies
  • HVL : SystemVerilog
  • HDL : Verilog
  • Assertion Based Verification: SVA
  • Universal Verification Methodology - UVM
  • Scripting Language: Perl
  • Operating System - Linux
  • Industry Standard Project
  • Business Communication

Elective Modules

  • DFT - Design For Testability

Sample Internship Projects

  • RISC-V RTL Design
  • AHB2APB Bridge RTL
  • PCS Subsystem RTL design
  • SPI IP core RTL Design
  • UART IP core RTL Design
  • RISC-V Verification in UVM
  • Bluetooth VIP in UVM
  • AHB UVC - Master agent in UVM
  • AHB2APB Bridge Verification in UVM
  • UART IP Verification in UVM
  • AHB UVC - Slave agent in UVM
  • PCS subsystem IP Verification - UVM
  • AXI UVC - Master agent in UVM
  • ICPIT Verification in UVM
  • AXI UVC - Slave agent in UVM
  • SPI IP Verification - UVM

EDA Tools

  • Mentor Graphics
  • Xilinx
  • Aldec

About the Instructor

The entire course is designed by CEO Mr. P R Sivakumar, a seasoned engineering professional with 20+ years of experience in Industry and Academia.

He has worked as a Verification Consultant for the top EDA companies Synopsys, Cadence and Mentor and helped various ASIC and FPGA design houses deploy and use various verification methodologies effectively, resulting in successful tape out of SoCs and Chips.

He now specializes in offering Verification IPs and consulting services, EDA flow development and corporate training on advanced ASIC verification methodologies and technologies. He is the recipient of the "Outstanding Technical Achievement" award from Cadence Design Systems and has delivered various corporate training courses at IBM, NXP, Cypress, Broadcom, Qualcomm, ST Micro, AMD, AvagoTech, Wipro, Samsung, etc.

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Have More Questions?

FAQ

About the course

What is the Blended VLSI RN course?

Blended means the best of both worlds. Our Blended VLSI RN course lets you learn at the comfort and safety of your house. It is specially designed for the final year or graduate/post graduate engineers to learn job oriented skills. This course offers training on VLSI Design, Verilog, SystemVerilog, Universal Verification Methodology along labs, and industry-standard projects. Placement assistance is also provided until you get a job.

How is the Blended VLSI course different from the Offline VLSI RN course?

Blended VLSI RN course offers you the combination of Online + Offline training as per your choice and convenience. Same course flow, same lab assignments, and also the experience of working on industry-standard projects. All at Home!

What is the duration of the Blended VLSI RN course?

The duration of the course is 6 months with 4 months of Online Training + 2 months of Project experience. You can do the project Online via VPN or at our campus in the labs. Completely your choice!

Admission

When can I apply for the Blended VLSI RN course?

We start accepting applications for the Blended VLSI RN course at Maven Silicon while you are in your pre-final/final year of graduation. Advise you to book your seats in advance, pertaining to limited admissions and increased demand.

What are the eligibility criteria for this VLSI course?

The undergraduates, graduates, or postgraduates from below streams can take up the course and make a career in VLSI Industry. BE/BTech in EEE/ECE/TE or ME/MTech/MS in Electronics/MSc Electronics.

Also, the eligibility criteria for securing admission in the Blended VLSI RN Course are 60% & more throughout your academics.

What is the Percentage/CGPA required for admission?

The eligibility criteria for securing admission in the Blended VLSI RN Course are 60% & more throughout your academics.

What are the prerequisite skills required to join this VLSI Course?

Digital Electronics and Basic Electronics are the prerequisite skills required to join this VLSI Course. You can also refresh and learn digital Electronics through our Online Digital Electronics course available at https://elearn.maven-silicon.com/digital-electronics

What are the steps involved in the admission procedure for the Blended VLSI RN course?

If you meet the eligibility criteria you can directly apply for the course here : https://www.maven-silicon.com/blended-vlsi-design-asic-verification

Career Opportunities

Is this VLSI course sufficient enough to enter into the VLSI Industry?

Absolutely! The Blended VLSI RN course gives you the exposure to Front end Design and gets you upskilled on ASIC Design Flow, Digital Electronics or Logic Design, CMOS Basics, PERL Scripting, Linux, Verilog HDL, FPGA Concepts, SystemVerilog HDVL, Static timing analysis, UVM methodologies, Assertion based Verification SVA along with hands-on experience around each subject. Along with that, you also get to work on multiple protocol-based and industry-standard projects.

What are the VLSI career opportunities after completing the Blended VLSI RN course?

Once you complete the course, you will become the right fit for a variety of roles in the semiconductor industry.RTL Design Engineer | FPGA Design Engineer | SoC Design Engineer | Digital Design Engineer | SoC Verification Engineer | AMS Verification Engineer | Application Engineer | ASIC Verification Engineer | DFT Engineer

Which has better career opportunities, Front end, or Backend VLSI?

The recent trends of VLSI design are more towards System on Chip designs. The scope of front end design verification has also increased from pure functional simulations to Formal verification, FPGA and other Emulation, Hardware and Software Co verification, etc.

With the recent emergence of Artificial intelligence, the Genetic algorithm and it's implementation towards VLSI Design opens up huge scope for Front end. So there are lots of opportunities for a front end design engineer in IP based design and System on Chip design areas.

To pursue VLSI Career in Frontend, which are the subjects to be focused on?

Basic Electronics, Digital Electronics or Logic Design, CMOS Basics, Verilog HDL, SystemVerilog HDVL, Static timing analysis, Universal Verfication Methodologies UVM, Assertion based Verification SVA

Course Delivery

Is there any free online VLSI course available?

Inexpensive courses with the utmost quality are our unique selling points. You can explore our courses at https://elearn.maven-silicon.com/

What kind of extra support will be given during the course?

"We train you both on technical and communication skills. Our regular Business communication classes help you to become all ready to crack interviews.Also, for all the modules of the Blended VLSI RN course, you get one year access to video tutorials through our learning managing system for extra revisions and practice. We also conduct periodic assessments, weekly knowledge checks, and aptitude tests on our elearn portal."

Can I do the labs and projects from home?

Yes, you can do the labs and projects from home as we provide 24/7 Lab access through VPN and installation of EDA tools on your laptop.

Do you train students to appear for interviews?

Absolutely. We work on imparting blended skills to our trainees. Apart from the technical classes, we have regular Business Communication classes. These classes focus on imbibing confidence, grooming you as professionals, and making you ready to express and present yourself in all kinds of interviews. Mock interviews are conducted for your practise also.

Is there any scope of completing the course before 6 months?

The Blended VLSI RN has been designed in a very compact manner that covers all the subjects, labs, and projects to make you a VLSI job-ready candidate. To complete all this before 6 months is difficult. But, you can still go ahead and try after the completion of 4 months of training.

Fees

When am I supposed to pay the fees?

As you register for the course, you will have to block your seat by paying the entire course fee at once.

What are the modes of payment?

Fees can be paid via NEFT/IMPS/ Debit Card/Credit Card/Mobile wallets/UPI payments.

Can I bring my laptop?

We are equipped with 250+ laptops/computers to support your learning process. Also, we strictly prohibit the use of your personal laptops/storage device in the premises under the copyright and trademark infringement act.

Infrastructure

Do you provide an internship with the VLSI companies?

You would take the inhouse internship with Maven Silicon where you will get the opportunity to work on projects which are simulations of industrial projects.

Internship

How does the internship at Maven work?

The internship at Maven Silicon is an integral part of the Course Curriculum. It lasts for 6 months. During this, you get to work on various industry-standard projects around Design and Verification. All this will make you Industry ready, experienced, and equip you with the required skill set.

Is it compulsory to complete the 6 months of the internship?

Absolutely not! During your internship, you get to attend multiple interviews as a part of the placement program. You shall be relieved from the internship as you get placed. If you complete your Internship, you would receive an Experience Certificate from us.

How does the internship at Maven work?

The internship at Maven Silicon is an integral part of the Course Curriculum. It lasts for 6 months. During this, you get to work on various industry-standard projects around Design and Verification. All this will make you Industry ready, experienced and equip you with the required skill set.

From when do I start getting the placement opportunities?

We recommend and provide placement support after the completion of 6 months of training. Click here for see our placement record https://www.maven-silicon.com/placement

Placements

Do you provide placements?

We provide 100% placement assistance to you and keep giving you job opportunities until you get placed. You can refer the link for the placement updates and know more about our hiring partners: https://www.maven-silicon.com/placement

Could I get placed even before I complete my training?

Yes. Our placement team starts offering job opportunities from the 5th month onwards. At times, our students get placed even before they complete their training.

For trainees who wish to complete their training first and then want to get placed will be offered job opportunities right after the training is finished.

What is the range of starting package for VLSI jobs?

The starting package may be in the range of 3-16 Lacs depending on the role and the company.

I have prior work experience of 1 year in a non-VLSI company. Will this help me in getting a VLSI Job after this training?

No, It will not add much value to your application for a VLSI role. However, with our training, you will have a strong profile for a variety of VLSI jobs i.e. RTL Design Engineer, FPGA Design Engineer, Verification Engineer, Design and Verification Engineer, SOC Verification Engineer, DFT Engineer, AMS Engineer, etc.

Will I go through technical and communication screening before facing the company interviews?

Yes. Every student goes through mock interviews and screening rounds before facing company interviews. This also helps us shortlist suitable candidates matching to client's requirement. For example, Some companies focus mainly on technical skills whereas others require engineers with excellent communication skills. It varies company from to company and profile to profile.

What is the reason few students get a lower package?

There are only two reasons behind a student getting a lower package or no job at all.

  • Poor technical skills
  • Poor communication skills

If someone does not have a strong grasp on theoretical and practical exposure of concepts or if he/she doesn't know how to explain it well, It is difficult for them to secure a job.

Where should I focus more - theory or labs?

You should focus on both. Without understanding the theoretical part of the concepts, you will not be able to apply them practically.

The Blended VLSI RN course has been designed and delivered to keep this in mind. Every day, you will start with theory sessions to learn and grip the concepts first and spend the latter half of the day in practicing the labs.

Do you guarantee a job after training?

We do not offer job guarantees to anyone. We guarantee you the best training which covers the entire design and verification flow. Our course structure, labs, and projects are well designed to help you navigate through the interview confidently. We also provide regular sessions on business communication which help you with your resume, LinkedIn profile, and lets you experience mock interviews. We are proud of the fact that our track record of placements is impressive and most of the top product and services companies hire from us.

Download the detailed curriculum of the course

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