SCAN COMPRESSION IN DESIGN FOR TESTABILITY

In Design for Testability (DFT), scan compression refers to the techniques used to reduce the test data volume and test time associated with scan-based testing of Integrated Circuits (ICs).

What is Scan Testing?

In scan-based testing, flip-flops in a digital circuit are connected into scan chains so that test patterns can be shifted in and out for structural testing (like stuck-at faults or transition delay faults). However, as chips get larger, scan chains get longer, and:

• The amount of test data (test vectors) becomes huge
• Test time increases

Tester memory and bandwidth requirements increases

What is Scan Compression?

Scan compression is a DFT technique that compresses test data before it enters the scan chains and decompresses it on-chip, or conversely compresses test responses before sending them off-chip.

Need for Scan Compression

Let’s take an example of a design that has 1000 scan elements (flip flops) and 10 scan in pins and 10 scan out pins. (Without Compression)

For one pattern, number of cycles required is 100 (shift_in) + 1 (Capture) + 100 (shift_out)

                                       =   201 test cycles

For 1000 patterns, 1000 x 201 test cycles = 201000 test cycles

If the same design is to be compressed by a factor of 10x, then there are 100 internal channels, which will have 10 flops in each chain. (With Compression)

For one pattern, number of cycles required is 10 (shift_in) + 1 (Capture) + 10 (shift_out)

                                       =   21 test cycles

For 1000 patterns, 1000 x 21 test cycles = 21000 test cycles.

How It Works

The following steps are involved in scan compression 

1. Sending compressed patterns from ATE to the chip
2. On chip Decompressor decompresses the incoming patterns and sends it to the scan chains
3. On chip Compressor compresses the incoming patterns and sends it to the tester
4. ATE checks if the received responses are matching with the expected responses or not. 

The Decompressor at the input side uses logic (combinational, sequential or combined) to expand the limited scan channels (pins) from the tester into the format required by the multiple internal scan chains. This logic can include multiplexer, XOR spreader or Adaptive Scan (DFTMax) or Linear Feedback Shift Registers (LFSR) or Fan out only (Illinois scan).

The Compressor at the output side reduces the data from the multiple scan chains back into a smaller number of scan channels for the tester. It is achieved through various algorithms and logic, which involves XOR trees or Multiple Input Signature Registers (MISR) before space compactor and other additional logics like masking logic, low power logic etc. to combine the data from multiple scan chains. 

Scan Compression Parameters 

• Test cycles = No. of patterns * Total No. of cycles for (Load + Capture + Unload)
• Test Time = Test cycles / Test clock frequency
• Test memory (input data storage) – Bits required for input/stimulus storage = 1 bit (Two values 0/1) = No. of Channels * Chain Length * No. of patterns
• Test memory (output data storage) – Bits required for output/response storage = 2 bit (Three values 0/1/X) = No. of Channels * Chain Length * No. of patterns * 2
• Test data volume = Input data storage + Output data storage
• Compression ratio = Number of internal scan channels / Number of external scan channels 

 Benefits of Scan Compression

• Reduced test data volume
• Reduced load/unload time of scan chains
• Reduced test cost and test time
• Lowers ATE (Automatic Test Equipment) memory and bandwidth requirements.
• Enables higher fault coverage with fewer test vectors

 Drawbacks of Scan Compression

• Extra cost is required on the additional hardware employed.
• Scan compression can lead to a reduction in test coverage, especially when targeting high compression ratios. 
• Higher compression ratios can result in an increase in the number of test patterns required, leading to “Pattern Inflation”.
• In a compressed scan chain, since the internal scan chains can’t be accessed directly, it leads to several debugging difficulties. 
• Scan compression increases the overall design complexity. 

    EDA Tools used for Scan Compression

Tool	Vendor	Compression Ratio	Notable Features
DFTMAX Compression	Synopsys	100x+	Power-aware test, integrated ATPG
Modus Scan Compression	Cadence	100x+	Dynamic X-masking, fast pattern generation
Tessent TestKompress	Siemens	100x+	Hierarchical DFT, advanced diagnosis
SpyGlass DFT	Ansys	N/A	DFT rule checking, scan readiness

These tools are essential for enabling efficient scan compression in modern ASIC/SoC designs. They are often used in combination with synthesis and layout tools to ensure that testability is built into the design from early stages.