Foundation Certificate Program in Design for Testing from iHub, IIT Roorkee
Where Elite Learning Fuels Elite Careers.
A proven track record
Years of Excellence
Years avg exp. of expert faculties
Industry Partners
Active Learners
About iHUB DivyaSampark, IIT Roorkee
iHUB DivyaSampark is a Section 8, not-for-profit Technology Innovation Hub at IIT Roorkee, established under the National Mission on Interdisciplinary Cyber-Physical Systems (NM-ICPS) by the Department of Science & Technology (DST), Government of India.
The hub is dedicated to fostering innovation in emerging technologies such as Artificial Intelligence, Machine Learning, Drones, Robotics, and Data Analytics, collectively known as Cyber-Physical Systems (CPS). iHUB aims to become a key enabler of next-generation digital products, services, and solutions across strategic national sectors including healthcare, Industry 4.0, smart cities, and defense.
Coordinated by a high-level inter-ministerial committee chaired by the CEO of NITI Aayog, and senior officials from DST, MeitY, and other ministries, iHUB DivyaSampark works to create an innovation-driven ecosystem by connecting researchers, entrepreneurs, industry, and academia.
Our Faculties
Sumit Mohanty
Technical Lead
13+ Years
Embedded System
Hemachandra Ramanath Bhat
Chief Technical Officer
37+ Years
Computer Architecture, SoC Design, Embedded Systems Design
Shaik Rafi Ahamed
Professor
20+ Years
Department of Electronics and Electrical Engineering, IIT Guwahati
Mr. Gaurav Trivedi
Program Coordinator and Expert
19+ Years
Department of Electronics and Electrical Engineering, IIT Guwahati
Sinduja K
Head - Technical Training
12+ Years
ASIC Verification
Dr Chiranjeevi G N
Senior Member Technical Staff
14+ Years
VLSI, PD
Basavaraj H
Technical Lead
11+ Years
Advanced Digital Design & RTL Design
Raghavendra Havaldar
Senior Member Technical Staff
18+ Years
RTL Design
Sumit Mohanty
Technical Lead
13+ Years
Embedded System
Hemachandra Ramanath Bhat
Chief Technical Officer
37+ Years
Computer Architecture, SoC Design, Embedded Systems Design
Program Highlights
About the Foundation Certificate Program in Design for Testing
The Foundation Certificate Program in Design for Testing (DFT) introduces learners to the essential principles of testability in VLSI and SoC design. The program explains how digital designs are created using Verilog HDL and how design decisions impact testability, providing a foundation for understanding manufacturing and reliability challenges.
Learners explore static timing analysis, physical design, fault models, scan chain insertion, automatic test pattern generation, test compression, boundary scan, and Built-In Self-Test (BIST). Case studies and examples demonstrate how DFT techniques ensure high fault coverage and production-ready chips.
This online program combines self-paced and live sessions, master classes from IIT faculty and industry experts, 24/7 lab and EDA tool access, iHUB DivyaSampark IIT Roorkee certification, and a capstone project to give learners practical exposure to DFT principles in real-world chip design.
What You Will Learn
VLSI SoC Design
- VLSI Technology Overview
- Moore’s Law
- IP, Subsystems, and Chips
- SoC Architecture
- SoC Design Process
- System-Level Design - Hardware & Software
- Semiconductor Industry Overview
Verilog HDL
- Introduction to EDA Tools
- Data Types
- Verilog Operators
- Advanced Verilog for Verification
- Assignments
- Synthesis Coding Styles
- Finite State Machine
- Design Consideration for DFT Implementation
- Hands-On Labs
Static Timing Analysis (STA)
- Types of Timing Analysis
- STA in Design Flow
- Different Timing Parameters
- Techniques to Improve Timing
- Timing Analysis Procedures
- Setup & Hold Time Violations
- Eliminate Setup & Hold Time Violations
- Demo on STA
Physical Design
- Design Styles
- Partitioning
- Floorplanning
- Placement
- Clock Tree Synthesis (CTS)
- Routing
- Static Timing Analysis (STA)
Design for Testability (DFT)
- Importance of Testing
- Outcome of Testing
- ASIC Design Flow & Testing
- Verification vs Testing
- Defect vs Fault
Automatic Test Pattern Generator (ATPG)
- Types of Testing
- Testing at Different Abstraction Levels
- Fault Modelling and Collapsing
- ATPG Basics
- Combinational ATPG
- Tessent Shell Introduction
- Fault Class
- Hands-On Labs
Fault Models
- Tessent Shell Usage
- Additional Fault Models
- Hands-On Labs
Scan Chain Insertion
- Introduction to DFT
- Scan Chain Insertion
- Hands-On Labs
Test Compression
- Test Compression Techniques
- Hands-On Labs
Boundary Scan
- Boundary Scan Architecture
- Boundary Scan Instructions
- Boundary Scan Applications
- Demo on Boundary Scan
Built-In Self Test (BIST)
- Introduction to BIST
- Logic BIST (LBIST)
- Memory BIST (MBIST)
- Demo on BIST
What Makes This Exclusive Collaboration a Benchmark in Learning Excellence?
Highly Rated Courses
Curriculum crafted and regularly updated by top semiconductor professionals, aligned with job market needs.
Superior Training Methodology and Infrastructure
Self-paced and live online classes with Q&A, featuring 70% hands-on learning through labs, mini-projects, and a final capstone project.
Course Completion Certificate
Earn an iHUB DivyaSampark,IIT Roorkee certified credential recognized by the semiconductor industry and showcase your verified skills to employers and recruiters worldwide.
Industry-Oriented Project
Solve real-world challenges with 24/7 lab and EDA tool access, and enhance your portfolio through impactful, project-based learning.
Value for Money
Get exceptional value for your investment with our budget-friendly offerings.
Masterclasses by IIT Faculty or Industry Experts
Exclusive masterclasses offering cutting-edge insights, real-world case studies, and advanced techniques to elevate your VLSI and Embedded Systems expertise.
Our Recruiters
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