Agenda
Introduction to Hardware Verification
Why SystemVerilog for Verification?
Key SystemVerilog HVL Concepts
Building a Simple SystemVerilog Testbench
Career Path in Verification
Q&A
Key Highlights
Understand why SystemVerilog is widely used for functional verification.
Learn the basic components of a modern verification testbench.
Get familiar with concepts like OOP, randomization and functional coverage.
Know the next steps to start learning SystemVerilog and verification methodologies.
Words From Our CEO’s Desk
My vision is to create an excellent learning ecosystem of superior technical expertise, hands-on training experience, and industry-oriented courses with innovative learning processes.
“I am thrilled to welcome you to our workshop at Maven Silicon! I am confident that this workshop will be a valuable learning experience for all of you.
We have put together an engaging agenda that covers the latest advancements in the industry. You will have the opportunity to learn from industry experts and gain experience with the latest tools and technologies.
At Maven Silicon, we are committed to providing high-quality training and helping individuals and organizations achieve their goals. We believe that this workshop is an excellent opportunity for you to develop VLSI skills and stay up-to-date with the latest trends in the industry. I wish you all the best for a productive and enjoyable workshop.“