SystemVerilog OOP – Polymorphism

Name: Maven Silicon
Brand: Maven Silicon
Rating: 4.7 (1481 reviews)

bySivakumar P R
June 4, 2020
1 minute read
6227 Views

This video explains how we use Object Oriented Programming feature Polymorphism to create SystemVerilog testbench which can generate various random test scenarios to verify the RTL design thoroughly.

To learn SystemVerilog in detail, please explore our online verification course at https://elearn.maven-silicon.com/vlsi-verification-systemverilog-uvm

Sivakumar P R
Sivakumar P R is the Founder and CEO of Maven Silicon. He is responsible for the company's vision, business, and technology. Sivakumar is a seasoned engineering professional who has worked in various fields, including electrical engineering, academia, and semiconductors for more than 25 years. Before founding Maven Silicon, he worked in the top EDA companies Synopsys, Cadence and Siemens EDA as a verification consultant.