Raghavendra H

Raghavendra Havaldar focuses on delivering high-quality training in VLSI design and RTL development at Maven Silicon. He has over 18 years of combined industry and academic experience and strong expertise in Verilog, RISC-V architecture, FPGA, GPIO, and AHB-APB protocols. He has played a key role in developing RTL for RISC-V cores and building self-checking testbenches, while also training hundreds of engineering graduates and professionals in frontend VLSI technologies