Name: Maven Silicon
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Putta Satish is in charge of providing expert technical guidance to the internal development team and enabling our learners across all training verticals. His articles help our VLSI aspirants learn and grow their knowledge in various VLSI topics.

Putta Satish

<img class="aligncenter wp-image-16408 size-medium" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/11/Blog-Banners-Rectangle-min-1024x576.png" alt="Practical Placement &amp; Routing Flow" width="1024" height="576" />

With the continuous and enormous increase in the complexity of modern-day chips, it is almost impossible for any chipmaker/IDM company to design an SoC from scratch. So, these chipmakers will depend on other IP (Intellectual Property) development companies for some of the sub-blocks and they will design the remaining sub-blocks on their own, for designing the complex SoCs as shown in the below figure. Using SoC design methodology, we integrate almost all these components/sub-blocks on a single die and fabricate it as a chip. To understand more about SoC, I recommend the readers, to go through the <a href="https://www.maven-silicon.com/blog/system-on-chip/">article on SoC</a>.

<img class="aligncenter wp-image-16405 size-medium" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/11/Asset-4@3x-1024x734.png" alt="Practical Placement &amp; Routing Flow" width="1024" height="734" />
Fig.1.1
The IPs that will be used while designing SoCs, will be available in different forms such as Soft macros, Firm macros, and Hard macros. Soft macros are the designs available in Synthesizable RTL form. Soft macros are not specific to any specific manufacturing process and are not targeted to any specific standard cell library. So, they offer more flexibility.

Firm macros are the designs available in the Gate Level Netlist form targeted to a specific library. During the design process of Firm Macros, they will be optimized for speed, power, and area. They are less flexible than soft macros and more flexible when compared with hard macros, since, the floorplan, placement, and routing within a firm macro can be customized by the designer.

Hard macros are generally available in GDS-II format which means the floorplan, placement, CTS, and routing are already done for these designs and they can be directly used as sub-blocks while designing the top-level SoC. So, they don’t offer much flexibility other than changing the orientation or changing the position and we can’t modify anything within a hard macro apart from accessing the I/O ports.  Examples of hard macros are memories and MP4 decoders etc, since they offer a single functionality. They would have been optimized for speed, power, and area already.

Designing complex chips such as SoCs with several IPs and our custom designs involves several processes as explained in the <a href="https://www.maven-silicon.com/blog/physical-design-flow/">article on Physical Design Flow</a>. In my previous <a href="https://www.maven-silicon.com/blog/practical-physical-synthesis-process/">article on Practical Physical Synthesis</a>, I have tried to explain the practical physical synthesis process in detail, and in this article, I will try to cover Placement &amp; Routing processes in detail. Placement &amp; Routing are very important steps in the design flow for achieving a compact, high-performance, and manufacturable chip design.

During the physical synthesis process, the synthesis tools will generate the gate-level netlist along with an initial floorplan for the Silicon chip to minimize multiple iterations between P&amp;R flow (Placement &amp; Routing flow) and Synthesis. During the initial floor-planning phase, the synthesis tool will determine the space for the I/O pins of the chip, position for hard macros, decide the power network, and the remaining area of the silicon chip will be dedicated for placing the standard cells corresponding to the synthesized netlist.

So, during the placement stage, the P&amp;R tool will determine the suitable location for all the standard cells on the floor area of the silicon chip. So, the objective of the placement process is, to find the optimal location of the standard cells that minimizes the area of the chip, power consumption, and signal delays while meeting the design constraints and satisfying the Design Rules. Overall QoR (Quality of Results) of the design greatly depends upon how well, the placement is done, because, based on the way, in which the placement is done, the following parameters will be affected.
<ol>
 	<li>Interconnecting wire length and wire delays.</li>
 	<li>Congestion in the routing network.</li>
 	<li>Power consumption of the chip.</li>
 	<li>Heat distribution across the chip.</li>
</ol>
<img class="aligncenter wp-image-16407 size-medium" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/11/Asset-5@3x-1024x605.png" alt="Practical Placement &amp; Routing Flow" width="1024" height="605" />
Fig.1.2
Once the placement is completed, the location of various standard cells will be fixed as shown in the above figure. Once the placement is completed, Clock Tree Synthesis (CTS) will be performed on the design to ensure that, the clock is distributed to various flipflops in the design with a minimum amount of clock skew. I will discuss about CTS process in detail in another article.

In the design flow, the subsequent process after completion of CTS is Routing. It involves connecting various standard cells and macros using the interconnecting wires to establish connectivity for achieving the required functionality. The objectives of routing are listed below.
<ol>
 	<li>Minimizing wire length: It will have an impact on reducing the wire delays which will improve the overall performance of the design.</li>
 	<li>Minimizing the congestion hotspots: Minimizing the congestion will help us to ensure that, signal integrity is maintained.</li>
</ol>
Various inputs required for the Physical Implementation (P&amp;R) tool for performing placement, CTS, and Routing are
<ol>
 	<li>Gate Level Netlist</li>
 	<li>Initial Floorplan (.def)</li>
 	<li>Libraries Used for Synthesis</li>
 	<li>Design Constraints (SDC)</li>
 	<li>Initial floorplan constraints.</li>
</ol>
<img class="aligncenter wp-image-16406 size-medium" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/11/Asset-6@3x-1024x666.png" alt="Practical Placement &amp; Routing Flow" width="1024" height="666" />
Fig.1.3
As shown in the above figure, the Gate Level Netlist, the initial floorplan, and the design constraints (SDC) will be derived from the Synthesis Process and additional constraints can be added, if required. After the completion of the Synthesis, the P&amp;R tool itself can perform placement, CTS, routing, optimization, and initial level Timing checks as well. If the timing requirements and other design constraints are not satisfied, the P&amp;R tool will optimize the design to ensure that, all the constraints are satisfied. If the area, power, timing, and congestion reports generated by the P&amp;R tool are not satisfactory or the timing requirements or other design constraints such as area and power are not satisfied, after all the possible optimizations during the P&amp;R Processes, then, we may need to go back to Synthesis for further optimization by imposing additional floor-planning constraints to the Synthesis tool.

After the successful completion of placement and routing processes, we will be able to generate the design library which contains the manufacturable layout (GDS-II). This GDS-II file can be used for signoff (Physical Verification) and the design library can be used for parasitic extraction by a dedicated Parasitic Extraction tool from EDA. The extracted parasitic information will be used to perform Timing Analysis in the later stages.

In this article, I have given an overview of the Practical P&amp;R Flow. If you are more interested in starting your career in VLSI Physical Design, you can learn and gain hands-on experience with Synopsys and Siemens EDA tools from our<a href="https://www.maven-silicon.com/physical-design-and-verification-course/"> Advanced Physical Design &amp; Verification Course</a>.

Practical Placement &#038; Routing Flow

<img class="size-medium wp-image-15284 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/03/Physical-Synthesis-Process-1024x576.png" alt="Physical Synthesis Process" width="1024" height="576" />

VLSI Technology is all about packing billions of transistors onto a single chip for creating complex SoCs. Designing these tiny chips containing very complex circuitry built with billions of transistors is not a simple job nor a one-step process. I strongly recommend the readers who are new to VLSI Physical Design should go through my previous article <a href="https://www.maven-silicon.com/blog/physical-design-flow/" target="_blank" rel="noopener">Physical Design Flow</a> before reading this article to understand the physical synthesis process.
<h1>What is Practical Physical Synthesis?</h1>
In this article, let me explain the Synthesis processes from a practical perspective. The list of different inputs required and outputs generated by the physical synthesis process is shown in the figure below.

<img class="size-medium wp-image-15298 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/03/physical-synthesis-process.jpg-1-1024x359.png" alt="physical synthesis process" width="1024" height="359" />

Since the modern-day ICs contain very complex circuitry, designing such complex circuits which contain millions of gates and flip-flops manually, is impossible. So, the design process is automated using Synthesis Process. Synthesis is a process of converting the RTL (Behavioural Register Transfer Level code) into an optimized Gate Level Netlist and finally, the synthesis process will map the gates and other digital logic blocks such as flipflops in the netlist with the equivalent blocks existing in the standard cell library.

<img class="size-full wp-image-15296 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/03/Synthesis.png" alt="Synthesis" width="386" height="43" />

The netlist generated by the synthesis tool will be used as input for the implementation(P&amp;R)  tool for performing floor planning, placement, and routing. But, if the routed netlist doesn’t meet the timing and power requirements, then we may need to go back to <a href="https://www.maven-silicon.com/blog/rtl-coding-synthesis/" target="_blank" rel="noopener">synthesis</a> and optimize the netlist again. This may lead to many no. of iterations between the synthesis tool and the P&amp;R[Placement &amp; Routing] tool which will delay the time to market. To minimize the no. of iterations between synthesis and P&amp;R tools, it is a good idea to do the initial level of floor-planning and placement during synthesis itself. The modern synthesis EDA tools are capable of generating Gate Level Netlist and initial floor-planning &amp; placement data which will be acting as input for the P&amp;R tool for more accurate placement and routing.

We will look into an example to understand more about Translation, Optimization, and Mapping in the later part of this article. During the Synthesis process, the standard cell library is one of the mandatory inputs to be supplied so that, it will be used in the Mapping process.

As mentioned earlier, VLSI Technology is all about packing billions of transistors onto a single chip for creating complex SoCs which will be used in highspeed computing, cloud systems, telecommunications, Automotives, defence, image and video processing, consumer electronics, Artificial Intelligence, etc. All the chips that will be used in a wide range of applications do not demand the same set of characteristics such as speed, area of the Silicon chip, Power consumption, and operating conditions.

For example, the chips that will be used in high-speed computing devices such as cloud servers, and Automotives, will demand the chips to work at high speed/frequency, consuming less power. But, the chips that are going to be used in portable and battery-operated gadgets such as smartwatches and other wearables, should not occupy more silicon area and should not consume more power, though the speed varies and it depends on the application. Similarly, the chips that will be used in applications, such as defence (radar equipment, sub-marines) and avionics should be designed in such a way that they can be operated in extreme climatic conditions such as high and low temperatures. So, the same type of logic cells such as gates, multiplexers, and flip-flops with the same characteristics (such as speed, area, power consumption, operating voltage, and operating temperature) are not suitable for all kinds of applications.

So, to meet the requirements of various applications as mentioned earlier, the standard cell libraries (which are available in PDKs[Process Design Kit] provided by foundries or library providers) come with predefined, pre-characterized logic gates and logic blocks in different variants. For example, if a standard cell library contains a two-input NAND gate, the same 2 input NAND gate will be available in multiple variants as listed below.
<ol>
 	<li>Multiple Driving Strength: Gates with lesser driving strength, will consume less power, and occupy a lesser area, but operate with a higher propagation delay when compared with the gates with higher driving strength. The standard cell library contains the same NAND gate with multiple driving strengths.</li>
 	<li>Multi-VT Cells: Similarly, the same NAND gate will be available with different threshold voltages such as LVT(Low Threshold Voltage), SVT (Standard Threshold Voltage), and HVT(High Threshold Voltage). LVT cells will have a lesser delay but operate with a higher leakage power consumption when compared with HVT cells.</li>
 	<li>Multi-Vdd Cells: Gates with higher Vdd can operate with high speed, but, they consume more power at the same time.</li>
 	<li>Multiple Operating Temperatures: Similarly, the same NAND gate will be available in different variants which are capable of working at different temperatures.</li>
</ol>
By looking at the library name, we can understand the characteristics of the logic cells available in a specific library. Please find below the table for the list of a few libraries that exist in a sample PDK from the foundry/library provider.

<img class="wp-image-15280 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/03/list-of-a-few-libraries.jpg.png" alt="list of a few libraries" width="647" height="272" />

Depending upon the requirements such as PPA[Power, Performance, and Area] of the IC, and operating temperature, we will guide the synthesis tool to use the gates/logic blocks from a specific target library, or sometimes, we will use logic cells from different libraries for different blocks in an IC. For example, we will use logic cells from a slower library in the non-critical paths of the circuit so that, power consumption can be reduced and we will try to use logic cells from a faster library in the critical paths of the circuit, so that, speed can be improved.

The synthesis tool will take decisions on “which of the logic cells must be used while generating a netlist based on the PPA requirement”. Along with the standard cell libraries and the RTL code, initial floor planning constraints and timing &amp; Power constraints (SDC) should also be supplied as additional inputs for the synthesis tools.

The initial Floor planning constraints file contains some constraints which will be used by the synthesis tool to take some of the decisions as described below.
<ol>
 	<li>The maximum area of the chip and the shape of the chip: With this constraint definition, the synthesis tool understands the maximum area that can be occupied by the chip. If the maximum area that can be occupied should be very minimum, the synthesis tool will use smaller logic cells with less driving strength.</li>
 	<li>Percentage of utilization: It represents the maximum area that can be utilized by the standard cell logic cells so that the remaining area of the chip can be used for routing the interconnecting wires in the future during the Routing stage. If the selected logic cells are utilizing more area when compared with this specified limit, then the synthesis tool will try to use much smaller logic cells from the library.</li>
 	<li>The exact location of some of the blocks or macros on the chip: With this constraint definition, the synthesis tool understands and determines the exact location of some of the blocks on the chip. Since the exact location of some of the blocks is determined during Synthesis itself, the synthesis tool can estimate the power and timing characteristics more accurately.</li>
</ol>
Similarly, the SDC file which will be defined to provide design intent such as maximum speed required and maximum power consumption of the chip contains the definitions of some constraints as described below.
<ol>
 	<li>Clock Time Period based on the maximum frequency required: with this definition, the synthesis tool can do an initial level of timing analysis and cross-checks, whether the netlist generated by the synthesis tool is working at the desired frequency without any setup and hold violations or not. This constraint will also guide the synthesis tool to decide which logic cell must be used (high-speed logic cell or low-speed logic cell) and to decide the location of various blocks. For example, if two or more logic blocks are placed very close to each other, then, the synthesis tool tries to place them far from each other in such a way that, the timing requirements and area requirements are still satisfied, so that, there is more space left between those blocks for proper routing without any congestion.</li>
 	<li>The clock uncertainties such as jitter, and operating conditions such as temperature: These constraints will help the tool to do the timing and power analysis more accurately.</li>
 	<li>The maximum allowable dynamic and leakage power: These constraints will help the tool to decide which logic cells (low-power cells or high-speed calls) to be chosen while generating the netlist.</li>
 	<li>Timing Exceptions such as multi-cycle and false paths: These constraints will guide the Timing Analysis Engine of the synthesis tool about the list of paths to be exempted from doing timing analysis and reporting the violations.</li>
</ol>
Now, let’s look into the following example RTL code to understand how exactly the synthesis process will go on. After initiating the synthesis process, the RTL code will be translated into a gate-level circuit as shown below (Step 1).

<img class="size-medium wp-image-15299 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/03/gate-level-circuit-1-873x1024.png" alt="gate-level circuit" width="873" height="1024" />

But, this direct translation uses 4 no. of D flip-flops and some logic gates with large fan-in like 4. Gates with larger fan-in are quite bigger in size and slower in operation. So, the synthesis tools will try to optimize the netlist as shown in step 2. Now, the optimized netlist requires only 1 flipflop and gates with a smaller fan-in as opposed to the netlist in the translation stage.

During the optimization, the synthesis tool will also try to reuse some of the partial outputs (for example – the partial output, (!d0 &amp; !d1) is reused for deriving both w2 and w3). This kind of reuse makes the whole gate level netlist with minimum gate count (lesser gate count implies lesser power consumption) and with a better speed.

Similarly, during the mapping stage (Step 3), the synthesis tool will map the logic blocks available in the optimized netlist, with the equivalent logic cells available in the library depending upon the requirements such as power, area, and speed as discussed earlier and generate an updated gate level netlist with the mapped cells from the library. If the standard cell library does not contain some specific blocks that are there in the optimized netlist, then the Synthesis tool will try to implement these blocks using the cells available in the standard cell library. For example, in the optimized netlist, there was a 4:1 Multiplexer and if the standard cell library doesn’t contain a 4:1 Multiplexer, then, the synthesis tool tries to implement it using 2:1 Multiplexers available in the standard cell library as shown in the above picture. Similarly, the library may not contain AND gate with inverted inputs which is there in the optimized netlist in step 2. So, the Synthesis tool will replace it with an equivalent 2-input NOR gate (U2) available in the library.

As you can observe in a sample Gate Level Netlist below, Synthesis Tool can use logic cells from different libraries with different characteristics such as LVT, HVT, and SVT depending on the area of the chip, speed required, and maximum amount of power consumption which are defined with the help of various constraints.

<img class="size-medium wp-image-15300 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2023/03/Gate-Level-Netlist-1-1024x547.png" alt="Gate Level Netlist" width="1024" height="547" />

Finally, as a result of the synthesis process, the following files will be generated as results along with timing and area reports.
<ol>
 	<li>Gate Level Netlist in Verilog HDL.</li>
 	<li>Final SDC: The constraint file with some additional constraints based on the logic cells chosen while doing synthesis. This will be an input constraint file for the implementation tool (For Placement and Routing) for estimating power and timing more accurately.</li>
 	<li>.def file: This netlist file contains the initial floor-planning and placement-related data which will be used by the P&amp;R tool to continue to do floor-planning and placement more precisely.</li>
</ol>
In this article, I have shared my insights into the Physical Synthesis process. If you are interested in starting your career in VLSI Physical Design, you can learn and gain hands-on experience with Synopsys and Siemens EDA tools from our Maven Silicon <a href="https://www.maven-silicon.com/physical-design-and-verification-course/" target="_blank" rel="noopener">Advanced Physical Design &amp; Verification Course</a>.

Practical Physical Synthesis Process

<img class="size-medium wp-image-15021 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/09/Physical-Design-Flow-1024x576.png" alt="Physical Design Flow" width="1024" height="576" />

VLSI Technology is all about creating complex chips and SoCs by packing billions of transistors into a single chip. The chips are extensively used in various sectors like data centres, telecommunications, automotive, defense, consumer electronics, industrial automation etc. Designing these tiny chips containing very complex circuitry built with billions of transistors is not a simple job, nor a one-step process. These chips, particularly ASICs can be designed by using either Full-Custom or Semi-Custom design methodologies.

In the case of Full Custom Design Methodology, it is required to design and verify all the logic components right from the transistor level, by customizing the length &amp; width of the transistors and by customizing how floor planning &amp; routing are done. This customization helps us to obtain the required characteristics in terms of power consumption, area of the chip, and propagation delays of the logic components. Since the pre-designed standard cells are not used in this methodology, design time, complexity, and cost for the design are more. So, this design methodology is best suited for mass production. In this methodology, SPICE Modelling is used for characterization.

In the case of Semi-Custom Design Methodology, pre-designed, pre-tested, and pre-characterized standard cells are used to design the circuitry by integrating additional components which are not available in the standard cell library. This design methodology will save a lot of design time, but the design will not be an optimized design with the required characteristics such as propagation delay, area, and power consumption. This design methodology can be used if the time to market is critical and for lesser quantities.

In this article, let me explain the full custom design flow which involves the physical design of transistors of the circuit and the interconnectivity between these transistors. <a href="https://www.maven-silicon.com/physical-design-and-verification-course" target="_blank" rel="noopener noreferrer">Physical Design</a> is a process of converting the RTL netlist into a layout that is manufacture-able (GDS). And this process of converting a netlist into a manufacture-able layout involves multiple steps as shown below.

<img class="size-full wp-image-15098 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/08/Process-of-converting-a-netlist-into-a-manufacture-able-layout.png" alt="Process of converting a netlist into a manufacture-able layout" width="462" height="651" />

Partitioning: It involves the decomposition of a complex circuit into smaller subsystems (sub-blocks) so that each subsystem will be of a manageable size and the no. of interconnections between these sub-blocks will be minimum.

Floor planning: In this step, the rough position of each block on the silicon chip and the shape of each block will be decided. And also, the pin locations of each block will be decided so that the interconnections between these blocks can be routed easily in the future as shown in the below picture.

<img class=" wp-image-15099 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/08/Floor-Planning-1024x708.png" alt="Floor Planning" width="666" height="460" />

Placement: In this step, the exact position of various sub-blocks will be decided with the objective of maintaining adequate space between various blocks, so that, Vdd and Ground supply lines and the interconnection wires can be routed in such a way that, there will be no clutter as shown in the above figure.

Clock Tree Synthesis (CTS): After the completion of floor planning and placement, millions of flip-flops in the complex circuit will be scattered at multiple places on the silicon chip, so that the transmission delays of the clock signal for all the flip-flops will not be the same. The clock will not arrive/reach all the flip-flops at the same time as shown in the figure below. The difference in the arrival times of the clock signal to these flip-flops is referred to as clock skew.

<img class="wp-image-15100 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/08/Clock-Tree-Synthesis-1024x382.png" alt="Clock Tree Synthesis" width="772" height="288" />

And it is mandatory to make sure that, the clock signal reaches multiple flip-flops with no or minimum skew difference. CTS will ensure that the clock reaches various flip-flops almost at the same time. In the clock tree synthesis process, any one of the standard Tree topology structures (shown in the below picture) will be implemented in the design with an intention of making the length of all the wires in the clock distribution network equal.

<img class=" wp-image-15101 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/08/Tree-topology-structures.png" alt="Tree topology structures" width="611" height="234" />

Routing: In this step, interconnecting wires between various blocks will be routed in such a way that, the length of the interconnecting wires will be minimum for meeting the timing requirements and for ensuring that, the chip area will not be increased as shown in the below picture. Proper routing will also ensure that there are no congestion hotspots in the chip so that, the probability of having faults during the fabrication will be less.

<img class=" wp-image-15102 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/08/Routing.png" alt="Routing" width="625" height="408" />

Static Timing Analysis:  Static Timing Analysis will be done on the final routed netlist which will represent/mimic the final layout of the chip that is going to be fabricated for validating the timing performance of the chip and to ensure that, the chip will meet the timing requirements such as maximum frequency of operation and the design works fine at the desired frequency without any setup and hold time violations.

<img class="wp-image-15103 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/08/Static-Timing-Analysis.png" alt="Static Timing Analysis" width="643" height="261" />

If the timing requirements are not met or if there are any setup and hold time violations identified, then, optimizing the placement and routing will be done, so that, timing may be improved, and violations will be eliminated.

Post the timing requirements are satisfied, the physical layout as shown below will be extracted, and these layouts will be used during the fabrication to prepare the required mask layers which will be used in the photolithography processes.

<img class="wp-image-15105 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/08/Physical-layout.png" alt="physical layout" width="638" height="334" />

Design Rule Check: The physical layout must obey the design rules imposed by the foundry to ensure that, the layout is manufacturable with a minimum no. of fabrication faults. They act as an interface or communication link between the circuit designer and the process engineer during the manufacturing phase. So, to ensure that the layout obeys all the design rules, a DRC will be done.

Layout Vs Schematic: Finally, to ensure that the design’s functionality is not altered during the physical design implementation Layout, the Layout Vs Schematic (LVS) equivalence checking as shown in the below picture will be done. This equivalence as shown below will be able to identify if there are missing device terminals or extra device terminals or unmatched devices and nets in the layout/schematic.

<img class="wp-image-15106 aligncenter" src="https://www.maven-silicon.com/blog/wp-content/uploads/2022/08/Layout-Vs-Schematic.png" alt="Layout Vs Schematic" width="598" height="438" />

Once this implementation flow which includes floor planning, placement, CTS, Routing, and Signoff flow with  DRC and LVS is completed, the final GDS-II file will be sent to the foundry where the actual silicon chips are created through a fabrication process using Silicon wafer.

As explained so far, the physical design flow contains several stages which require the effort of many skilled VLSI engineers at each stage. So, the demand for skilled VLSI Physical Design Engineers will continue to grow as the demand for ICs is raising at a fast pace.

If you're aspiring to become a Physical Design &amp; Verification Engineer, <a href="https://elearn.maven-silicon.com/course/VLSIPhysicalDesignCourse-168">VLSI Physical Design Course</a> with 100% placement assistance.

Putta Satish

Principal Engineer

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Putta Satish

Principal Engineer

All Posts

Practical Placement & Routing Flow

Practical Physical Synthesis Process

Physical Design Flow

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Subscribe to our Blog

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Get trained online as a VLSI Professional

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