UVM SoC Testbench

Name: Maven Silicon
Brand: Maven Silicon
Rating: 4.7 (1481 reviews)

bySivakumar P R
May 15, 2020
1 minute read
7891 Views

This video explains how we reuse the IP level UVM test benches at the SoC [System on Chip] level, reusing the IP level UVM sequences to generate various SoC level test scenarios.

To learn SystemVerilog in detail, please explore our online verification course at https://elearn.maven-silicon.com/vlsi-verification-systemverilog-uvm

Sivakumar P R
Mr. P R Sivakumar is the Founder and CEO of Maven Silicon and Aceic Design Technologies, leading vision, strategy, and technology. With over 28 years of experience across academia and the semiconductor industry, he has worked with companies like Synopsys, Cadence, and Mentor Graphics, supporting advanced verification and successful chip tape-outs. He focuses on Verification IPs, consulting, EDA flow development, and corporate training. A thought leader and author, he contributes to industry platforms. He has received multiple honours, including Cadence’s Outstanding Technical Achievement award, and holds a degree in Electrical and Electronics Engineering from Madurai Kamaraj University.