When Verification Leads

We electronics engineers always assume that the verification is a secondary process like software testing, but in chip design process the verification is critical and it’s going to even lead the design in the future. Excerpts of this conversation can help you to understand how the verification will lead the design in the future:  https://semiengineering.com/when-verification-leads/

In present scenario, the chip verification is critical and unavoidable. We don’t want to fabricate the chips which can’t be verified. Similar to DFT [Design For Test] , we are also making the design verifiable with DFV [Design for Verification]. Also the new approaches like Portable Stimulus Standard [PSS] will address the issues of system level verification spec defined in the English language. 

The future is the dream of producing the design directly from the high level abstract models like PSS. What we think of today as a verification code would become the source of the design. 

Is there a possibility of synthesis that can do all of that for you? Can synthesis advance to the point where it can take a very high-level model, call it verification, call it design, and produce a fully elaborated design from it? That is a huge leap.

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