Sanjay Chowdhary

Sanjay V. Chowdhary is a Senior Member of Technical Staff at Maven Silicon with over 16 years of experience in VLSI verification and technical education. He specializes in delivering advanced training in SystemVerilog, UVM, RISC-V, and AMBA, empowering engineering students, graduates, and professionals with industry-ready semiconductor skills. His expertise includes HDL/HVL languages such as VHDL, Verilog, and SystemVerilog, UVM methodology, and processor architectures including RISC-V and ARM V8-A. He has contributed to multiple verification projects involving Dual Port RAM, routers, RISC-V SoCs, and AHB bridge verification. Passionate about simplifying complex technical concepts, Sanjay leverages mnemonics, one-liners, and visual learning approaches to make VLSI verification more engaging and accessible. Currently pursuing his Ph.D. at VTU Belagavi, he continues to combine research, teaching, and hands-on verification experience to mentor and inspire the next generation of semiconductor professionals.