DFT: Scope, Techniques & Careers

DFT Scope and Techniques

What is DFT?

DFT, Design for testing/testability is a design methodology which defines the IC design techniques that add testability features to a hardware design. DFT improves the observability and controllability of the hardware design which could be an IP/Sub-system/chip/SoC usually referred as Design Under Test [DUT], during hardware testing.

Why DFT?

Like how we verify the functional correctness of the DUT during simulation, we also generate manufacturing tests and do testing on the fabricated silicon to detect fabrication/manufacturing faults. We use Automatic Test Equipment [ATE] for hardware testing.

Let me walk you through various DFT techniques in this article.


Automatic Test Pattern Generation [ATPG] is an automated algorithm used by EDA tools to generate test patterns. The test patterns generated are used by the Automatic Test Equipment [ATE] for hardware [DUT] testing. The ATE runs all the test patterns to identify the working chips for the shipment, by identifying and removing the defective silicon.


SCAN is a DFT design technique used to improve the overall testability of a chip. Using SCAN all the flip-flops can be connected as a scan chain and tested during hardware testing.

Scan Chain: The scan cells are inserted into a gate level netlist which replaces the regular DFF with scan cells i.e. mux-based D scan cell without changing the functionality of the DUT [RTL Design]. Now all the scan cells can be connected as a scan chain.

Circuit before and after scan insertion

In this approach, the DFT scan tool applies scan design rules, and then scan configuration followed by scan stitching. Finally, a modified netlist is created. Then scan reordering is done with the help of Placement & Route tool and then final netlist is generated. On this updated netlist, test patterns are generated with the help of ATPG.

Test Compression

Test Compression DFT technique involves compressing the amount of test data (stimulus and response) that must be stored on the Automatic Test Equipment [ATE] for testing, from the ATPG generated test-set. This technique reduces the amount of tester memory required and reduces the testing time. Compressed test data can be quickly transferred from the tester to the chip efficiently using even low bandwidth serial interfaces.

Test Compression

Boundary Scan

Boundary Scan DFT technique is basically used to test the interconnections of the sub-blocks within an IC or ICs at the board level. It is based on the idea of scan design, which is used to insert boundary scan cells across the I/O buffers of the chip. This technique uses JTAG standard to do the hardware testing.

The boundary scan cells provide scan paths in the form of a scan chain which provides the ability to shift-in the test vectors to be applied through the pad to the pins and interconnections on the PCB. The output responses are captured at the input buffers on other chip on the board and shifted-out for fault detection.

Boundary Scan


Built-in-self-test is a DFT technique which is used to enable the chip to generate test patterns on its own for its logic circuit testing.

Two types of BIST are:

  1. Logic BIST [LBIST]
  2. Memory BIST [MBIST]

Logic BIST is used to test a sequential or combinational circuit where LFSR (Linear feedback shift register) logic is used to generate Pseudo random test patterns for testing the circuit. Also, it has built-in response analyser to compare the responses captured with a golden reference value. LBIST controller within the chip controls the overall operation.

Logic BIST

Memory BIST is used to test an embedded RAM using memory algorithms like March & Checkerboard algorithms. In this case, the MBIST logic can shift out the address of any faulty cell, column, or row to the external tester by the scan facility. The Memory BIST is inserted at the RTL level. Different components of MBIST are Memory interface, MBIST controller, and BIST Access port.

DFT Career

Design for Testability in VLSI is an interesting domain in VLSI as functional verification. Like functional verification, hardware testing is equally essential for successful working silicon. DFT is a fast-growing field, evolving with new innovative design and EDA techniques. VLSI Engineers with DFT domain expertise are in huge demand as the semiconductor industry is growing fast, producing more and more complex chips and SoCs for the IoT and AI applications.

Electrical/Electronics engineers who love to creatively deal with logic circuit design can choose the DFT in VLSI domain and shine in the semiconductor industry as verification engineers who deal with complex OOP programming in HVLs for chip verification. The industry needs both Verification and DFT engineers and treats them equally important. We hope you will be the next smart DFT engineer we have been searching for.

Aspiring to become a DFT engineer? Explore our Job-Oriented Advanced VLSI Design and DFT Course with hands-on project experience and 100% placement assistance – https://www.maven-silicon.com/advanced-vlsi-design-and-dft-course

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Technical Lead
Susmita is focused on delivering effective training to the learners in front-end RTL design and Design for Testability and she writes articles that help our readers gain good knowledge on such VLSI topics.