This video explains how to write a synthesizable Verilog program for the half adder and implement the full adder using the same through Verilog module instantitation. Also it helps you to understand the concept of module instantiation and how we build any IP/Chip hierarchically.
In this video blogging series, we will be explaining the Verilog coding style for various building blocks like Adder, Multiplexer, Decoder, Encoder, ALU, Flip-Flops, Counter, RAM and FSM. Understanding the coding style of all the building blocks will help you to implement any sub-system or IP in Verilog HDL as a RTL programming expert. Stay tuned!