UVM provides TB framework and base class library to create the verification environment in SystemVerilog. You can consider UVM as a testbench methodology for creating the class-based verification environment in SystemVerilog. So, you should be the expert user of all SystemVerilog [SV] language features, like Object Oriented Programming, randomization, functional coverage, interfaces, mailbox, semaphores, assertions, etc. for the RTL design verification. There are many online/offline training courses and textbooks are available in the market and I recommend some of the best for your reference. Most of the best textbooks available in the market explain the concepts and language features well but they don’t focus on right TB architecture, verification planning, complete env implementation, etc. So, you can think of referring good textbooks and LRMs only while working on the project, during coding phase.
Maven Online SystemVerilog Course:
With the SV coding expertise, you can learn the UVM concepts at https://verificationacademy.com/
UVM user Guide:
Beginner: SystemVerilog for verification by Chris Spear
Advanced: Writing Testbenches in SystemVerilog by Janick Bergeron