Creating Tests the PSS Way in SystemVerilog

Portable Stimulus is one of the latest hot topics in the verification space. Mentor, and other vendors, have had tools in this space for some time, and Accellera just recently released the Portable Test and Stimulus Standard, a standard language that can be used to capture Portable Stimulus semantics.

From the name, one very obvious application of Portable Stimulus is to enable a test scenario to easily be reused across test-execution platforms or levels of verifica-tion. Portable Stimulus does allow test intent to be reused from block level to subsystem level to SoC level. It also enables a Portable Stimulus tool to create the tests that are appropriate for the variety of test platforms on which that verification is carried out – typically SystemVerilog for block and subsystem level, and C tests for SoC level.

However, Portable Stimulus enables more than just test portability. Portable Stimulus enables a high degree of automation in the test creation process, and enables the user to describe tests at a far higher level of abstraction than is possible with techniques like SystemVerilog and UVM.


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