Is it worth reading SystemVerilog LRM?

Language Reference Manual is the main source of reference for everyone, EDA vendor, Design & Verification Engineer, Training vendors, etc. For example, how the simulator should simulate the SystemVerilog code, especially the event scheduling algorithm, is defined by LRM. Engineers must have the habit of referring to LRM while writing the source code.

It’s a reference manual, so don’t use it as a textbook to understand “How to use SystemVerilog to create the class-based verification environment”. You may want to refer to the textbooks or learn through training courses. At the same time, don’t focus on language syntax while learning, you can always refer to the LRM while writing the source code.

We have published an Online VLSI Verification Course. This course will help you to understand the Verification Methodologies and SystemVerilog[SV] language concepts and grow as an expert user SV.

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