Test Plan is a traditional term primarily used for the directed test cases that we used to create in HDL – Verilog/VHDL. But in SystemVerilog [SV], we create random test cases, as the language supports constraint random simulation. In the case of random simulation, we define the verification plan primarily based on the design [DUT] features using functional coverage. Verification Plan [Vplan] defines how the DUT features have to be verified using functional coverage. Vplan will not have any details about the test cases, because we do not have details of random test cases during the planning phase. During the random simulation, all the DUT features will be covered in a random sequence. So, we use functional coverage to track the simulation progress. This verification methodology is called CRCDV, Constraint Random Coverage Driven Verification. You can learn it from our online course Verification Methodology Overview
But, in HDL we create a directed test case for every DUT feature. So, the plan will have the details of all test cases. And hence, it is called a test plan. In the industry, still traditional experienced engineers & managers may refer to the Vplan of SV TB as a test plan, like how we casually interchange the terms DUT and DUV.
I have explained the concept of CRCDV, functional coverage, and SV TB implementation very well in our online VLSI Verification course.