Analog circuit design still happens at the layout level. The layout engineer places and connects all the analog components and creates the layout using EDA tools. The generated layout will be verified through a process called physical verification that involves a series of checks like Design Rule Checking[DRC], Layout versus Schematic[LVS], Parasitic Extraction, Antenna rule checking and Electrical Rule Checking[ERC].
Post physical verification, the final verified netlist data GDSII will be sent to the foundry which generates photomasks from the GDSII and fabricates the chip.
We use Verilog AMS primarily to create the analog functional models [non-synthesizable] and run mixed signal simulation to verify the functionality of any IP/Chip that uses both digital and analog components. Most of the time, the top-level IP/Chip level testbench might be in Verilog/SystemVerilog. So, I would say a very good Verilog programming expertise will help a beginner to learn Verilog AMS and SystemVerilog in the future and manage such Analog Mixed Signal simulation at the IP/Chip level.
To do the analog layout design, you should be very good at analog design concepts and analog layout design using EDA tools. Verilog HDL programming expertise will definitely be an added advantage.