As a verification engineer, you should be good at finding bugs in the design and disproving the designer, while verifying and proving the design [DUT/DUV] functionality as per the specification. So, we prefer verification engineers who can understand the design very well and verify it smartly. This is what we expect you to prove in the interview and convince us to bag the job offer. Let me enumerate the important things that can help you to convince the interviewer with immense confidence naturally and walk away with the job offer.
- Design Concepts: Though you want to become a verification engineer, you still need to be extremely good at design fundamentals: Digital Electronics, RTL design & coding, etc. Your design expertise helps you to deal with DUT specification, Test/Verification Plan, TB architecture, etc., especially Simulation debugging. You can’t debug the simulation failures and communicate the design bugs/issues to the designer without understanding the design functionality. More than 60% of your time will be spent on debugging the simulation failures.
- Verification Methodologies & Languages: Learn the methodologies like CRCDV [Constraint Random Coverage Driven Verification], UVM [Universal Verification Methodologies], and the languages i.e. SystemVerilog. We use them primarily to verify the complex and technology independent IPs & sub-systems which could be used for both FPGAs & ASICs. Nowadays we expect the FPGA folks to also be good at all these latest verification methodologies, as the FPGA has also grown equally complex.
- Verification Process: Understand the complete verification process:
Verification Plan [TB architecture, Coverage Model, Self-Checking strategies, Scenarios, etc.] –> TB coding –> Testcases –> Regression Testing –> Simulation Debugging –> Coverage Closure –> Test Suite Optimization, etc.In order to understand the complete verification process, gain the experience of working on any protocol-based project like implementing AHB & APB UVCs and verifying the AHB-to-APB bridge RTL. Also, working knowledge of any standard simulator will be an added advantage.
- Knowledge & Experience: To gain more confidence, learn more protocols like AHB, SPI, UART, I2C and understand the basic architecture of any standard processor e. RISC-V/Micro-controller. You can download the open-source RTL code of some of these processors and verify them. Also, work on more projects independently and gain good coding expertise in HDL and SystemVerilog. Knowledge in PERL and C programming will be an added advantage, as it helps you to deal with any SoC verification environments.
- Approach: Blindly learning the language syntax, protocols, writing programs and running simulation on multiple EDA tools will not help you to get the job. In any technical interview, usually, we start with design basics, especially for the fresh engineering graduates. Once we are convinced that you are good at design concepts, then only we would be interested to check whether you are good for verification. So, we expect you to be skilled at the basics i.e. Digital, Analog, CMOS as a talented electronics engineer who aspires to be a part of the Semiconductor Industry.