Why do we prefer Packets/Transactions to create SV TB as a TLM?

In SystemVerilog, you can define the transaction[packet/frame] using class data type. But you should know why we prefer transactions to implement SV TB as a TLM[Transaction Level Model].

If you don’t have an operating system like Windows/Linux, then you may want to write the assembly program to use your PC. Also, you prefer Windows than Linux because of its GUI based user interface since Linux is mostly a command-based interface. So, whatever you do on your PC, eventually everything happens in terms of processor instruction sets, but on the chip, finally it happens in terms of binary. Binary is the lower level of abstraction, meant for IC. So, we created different layers like OS[Windows] -> Processor assembly instructions -> Binary. As a user, you need a higher-level interface like OS [Windows] to use the PC.

Similarly, in verification, we create higher-level user interfaces for the test case writers to write the test cases in terms of packets. So that he/she can easily think of writing various test cases to generate different kinds of real-time scenarios during a simulation. For example, to verify a mobile SoC, you may want to generate real-time scenarios like receiving SMS while watching a video, attending a call while listening to music, receiving multiple messages while talking on a conference call. If you think of your real-time situation, everything happens randomly. So, you really need a higher level of abstraction to verify complex SoCs.

In this case, the abstraction could be:

Scenarios [Testcase: Receiving SMS while watching video] -> Sequence of Packets [SMS packets + Video Packets] -> Packets [Driver drives packet by packet] -> Binary [DUT]

Packet is nothing but a bunch of binary values. We use packets to define different kinds of scenarios during a simulation. So, as a verification engineer, you need to understand how to implement a testbench that can do everything in terms of packets and provide a higher level of user interface. Your testbench will be used by multiple testcase writers. This helps the testcase writers to write all the testcases in terms of packets. This is the main learning objective of our online verification course and this is what you learn and explore in VLSI Verification – How to implement the class-based SV testbench [Verification Environment].