How do I get a job in ASIC/FPGA verification?
As a verification engineer, you should be good at finding bugs in the design and disproving the designer, while verifying and proving the design [DUT/DUV] functionality as per.
Day: June 4, 2020
SystemVerilog OOP – Polymorphism
This video explains how we use Object Oriented Programming feature Polymorphism to create SystemVerilog testbench which can generate various random test scenarios to verify the RTL.
How can you be a great blogger?
To know the secret, ask yourself, ‘Why do we need a blog?’. The blog helps us communicate to the world who we are, displaying our strong domain expertise and differentiating ourselves as a uniqu...
