How did our Blended VLSI course lead Subashini to success?
This video explains why we prefer Object Oriented Programming to create the class-based verification environment in SystemVerilog...
Year: 2020
Maven Silicon – a RISC-V Training Partner
We are delighted to collaborate with RISC-V and empower the engineering community to innovate and create new and powerful chips, primarily using open.
First Job! Are you all equipped?
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Sit down. Calm down!
Newsletter August 2020
The world in the last quarter has seen a massive change with a significant impact on businesses. Needles to say, the Learning and Development Industry has taken this challenge head-on! Here is our st...
Maven Silicon featured in Business India Magazine
Business India magazine interviewed our Founder and CEO Mr. P R Sivakumar, VP Mr. Catakam Kumar, and our alumnus, and published this article meritoriously.
It beautifully narrates our founder’s jo...
SystemVerilog – Class based Verification environment
This video explains why we prefer Object Oriented Programming to create the class-based verification environment in SystemVerilog...
Verification IP Vs Testbench
Anyone can create a testbench and verify the design, but it can’t be simply reused as a verification IP. Most of the module/IP level testbenches are used once to verify the design. We always want t...
Where are we heading in the Semiconductor business?
I am glad to address this question and explain to those who might always be wondering and asking everyone in the industry ‘Where are?’
Code Coverage
Though we use both code and functional coverage to sign-off the design verification, they are not the same. So, you need to understand what is code coverage and how it is used to improve the quality.
5 habits of a Job Seeker
Looking for a Job?
How is it going?
Naah! Not really smooth?
Already tired and frustrated?
Well! Hold on.
Sit down. Calm down!
