Have you come across a post on any social media platform, wherein the post is hardly 100 characters, but what takes most of the space is the series.
This video explains why we prefer Object Oriented Programming to create the class-based verification environment in SystemVerilog...
Anyone can create a testbench and verify the design, but it can’t be simply reused as a verification IP. Most of the module/IP level testbenches are used once to verify the design. We always want t...
I am glad to address this question and explain to those who might always be wondering and asking everyone in the industry ‘Where are?’
Though we use both code and functional coverage to sign-off the design verification, they are not the same. So, you need to understand what is code coverage and how it is used to improve the quality.
Looking for a Job? How is it going? Naah! Not really smooth? Already tired and frustrated? Well! Hold on. Sit down. Calm down!
It’s definitely worth it, but not mandatory to get into the semiconductor industry. SystemVerilog is the most preferred language for the IP & Sub-system verification that demands constrained.
As a verification engineer, you should be good at finding bugs in the design and disproving the designer, while verifying and proving the design [DUT/DUV] functionality as per.
This video explains how we use Object Oriented Programming feature Polymorphism to create SystemVerilog testbench which can generate various random test scenarios to verify the RTL.
To know the secret, ask yourself, ‘Why do we need a blog?’. The blog helps us communicate to the world who we are, displaying our strong domain expertise and differentiating ourselves as a uniqu...