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  • 2020
  • June

Month: June 2020

SystemVerilog – Class based Verification environment

June 17, 2020October 8, 2020 Sivakumar P R
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This video explains why we prefer Object Oriented Programming to create the class-based verification environment in SystemVerilog...
Verification Videos 

Verification IP Vs Testbench

June 16, 2020October 8, 2020 Sivakumar P R
Anyone can create a testbench and verify the design, but it can’t be simply reused as a verification IP. Most of the module/IP level testbenches are used once to verify the design. We always want t...
Blog Verification 

Where are we heading in the Semiconductor business?

June 13, 2020October 8, 2020 Sivakumar P R
I am glad to address this question and explain to those who might always be wondering and asking everyone in the industry ‘Where are?’
Blog VLSI Industry 

Code Coverage

June 10, 2020June 17, 2020 Sivakumar P R
Though we use both code and functional coverage to sign-off the design verification, they are not the same. So, you need to understand what is code coverage and how it is used to improve the quality.
Blog Verification 

5 habits of a Job Seeker

June 6, 2020June 17, 2020 Sweety Dharamdasani
Looking for a Job? How is it going? Naah! Not really smooth? Already tired and frustrated? Well! Hold on. Sit down. Calm down!
Blog VLSI Training 

Is it worth learning SystemVerilog in college itself?

June 5, 2020June 5, 2020 Sivakumar P R
It’s definitely worth it, but not mandatory to get into the semiconductor industry. SystemVerilog is the most preferred language for the IP & Sub-system verification that demands constrained.
Blog Verification 

How do I get a job in ASIC/FPGA verification?

June 4, 2020June 16, 2020 Sivakumar P R
As a verification engineer, you should be good at finding bugs in the design and disproving the designer, while verifying and proving the design [DUT/DUV] functionality as per.
Blog Verification 

SystemVerilog OOP – Polymorphism

June 4, 2020June 5, 2020 Sivakumar P R
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This video explains how we use Object Oriented Programming feature Polymorphism to create SystemVerilog testbench which can generate various random test scenarios to verify the RTL.
Verification Videos 

How can you be a great blogger?

June 4, 2020June 5, 2020 Sivakumar P R
To know the secret, ask yourself, ‘Why do we need a blog?’. The blog helps us communicate to the world who we are, displaying our strong domain expertise and differentiating ourselves as a uniqu...
Blog VLSI Training 

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Maven Silicon
  • Home
  • About Us
    • About Us
    • CEO’s message
    • Partners
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  • Blog
  • Admissions
    • Application
    • Training Calendar
    • Online Test
  • Program Offerings
    • Job Oriented Course
      • Advanced VLSI Design and Verification Course – [VLSI RN]
      • Blended Learning VLSI Program – [Blended VLSI RN]
      • Advanced ASIC Verification Course – [VLSI VM]
    • Corporate Training
    • Online VLSI Courses
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