What are the coding skills required for an analog circuit and layout design engineer?
Analog circuit design still happens at the layout level. The layout engineer places and connects all the analog components and creates the layout using.
Category: Verilog HDL
Verilog Programming Series – Finite State Machine
This video explains how to write a synthesizable Verilog program for a simple sequence detector, following the FSM coding style in Verilog. In this video blogging series, we will be explaining the Ve...
Verilog Programming Series – Dual Port Synchronous RAM
This video explains how to write a synthesizable Verilog program for Dual Port Synchronous RAM, using Verilog parameters. In this video blogging series, we will be explaining the Verilog coding style...
Verilog Programming Series – Modulo-12 Counter
This video explains how to write a synthesizable Verilog program for Modulo-12 loadable counter and how to define the priorities of various control signals. In this video blogging series, we will be ...
Verilog Programming Series – D Flip-Flop
This video explains how to write a synthesizable Verilog program for DFF. Also, it explains the coding style for different implementations like synchronous and asynchronous reset/clear. In this vid...
Verilog Programming Series – Arithmetic Logic Unit
This video explains how to write a synthesizable Verilog program for ALU, using Verilog parameters and operators. In this video blogging series, we will be explaining the Verilog coding style for ...
Verilog Programming Series – 2 to 4 Decoder
This video explains how to write a synthesizable Verilog program for 2to4 Decoder using the ‘case’ statement and the importance of default statement while implementing the combinational logic. ...
Verilog Programming Series – 4 to 2 Priority Encoder
This video explains how to write a synthesizable Verilog program for 4to2 Priority Encoder using the ‘if-else’ statement. Also, it explains the coding style difference ’Case’ Vs ‘if-else’...
Verilog Programming Series – 4 to 1 MUX
This video explains how to write a synthesizable Verilog program for 4to1 multiplexer using the ‘case’ statement and the importance of default statement while implementing the combinational logic...
Verilog Programming Series – Full Adder
This video explains how to write a synthesizable Verilog program for the half adder and implement the full adder using the same through Verilog module instantiation. Also, it helps you to understand ...
